Commit 661f78d8 authored by Leo Chen's avatar Leo Chen Committed by Russell King

ARM: 5646/1: bcmring: add mach-bcmring/mm.c and memory headers

memory map addresses
memory map description and init functions
Signed-off-by: default avatarLeo Chen <leochen@broadcom.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b7462d65
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file mm_addr.h
*
* @brief Memory Map address defintions
*
* @note
* None
*/
/****************************************************************************/
#ifndef _MM_ADDR_H
#define _MM_ADDR_H
/* ---- Include Files ---------------------------------------------------- */
#if !defined(CSP_SIMULATION)
#include <cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* Memory Map address definitions */
#define MM_ADDR_DDR 0x00000000
#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
#define MM_ADDR_IO_FLASHC 0x20000000
#define MM_ADDR_IO_BROM 0x30000000
#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
#define MM_ADDR_IO_DMA0 0x30200000
#define MM_ADDR_IO_DMA1 0x30300000
#define MM_ADDR_IO_ESW 0x30400000
#define MM_ADDR_IO_CLCD 0x30500000
#define MM_ADDR_IO_PIF 0x30580000
#define MM_ADDR_IO_APM 0x30600000
#define MM_ADDR_IO_SPUM 0x30700000
#define MM_ADDR_IO_VPM_PROG 0x30800000
#define MM_ADDR_IO_VPM_DATA 0x30A00000
#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
#define MM_ADDR_IO_CHIPC 0x80000000
#define MM_ADDR_IO_UMI 0x80001000
#define MM_ADDR_IO_NAND 0x80001800
#define MM_ADDR_IO_LEDM 0x80002000
#define MM_ADDR_IO_PWM 0x80002040
#define MM_ADDR_IO_VINTC 0x80003000
#define MM_ADDR_IO_GPIO0 0x80004000
#define MM_ADDR_IO_GPIO1 0x80004800
#define MM_ADDR_IO_I2CS 0x80005000
#define MM_ADDR_IO_SPIS 0x80006000
#define MM_ADDR_IO_HPM 0x80007400
#define MM_ADDR_IO_HPM_REMAP 0x80007800
#define MM_ADDR_IO_TZPC 0x80008000
#define MM_ADDR_IO_MPU 0x80009000
#define MM_ADDR_IO_SPUMP 0x8000a000
#define MM_ADDR_IO_PKA 0x8000b000
#define MM_ADDR_IO_RNG 0x8000c000
#define MM_ADDR_IO_KEYC 0x8000d000
#define MM_ADDR_IO_BBL 0x8000e000
#define MM_ADDR_IO_OTP 0x8000f000
#define MM_ADDR_IO_I2S0 0x80010000
#define MM_ADDR_IO_I2S1 0x80011000
#define MM_ADDR_IO_UARTA 0x80012000
#define MM_ADDR_IO_UARTB 0x80013000
#define MM_ADDR_IO_I2CH 0x80014020
#define MM_ADDR_IO_SPIH 0x80015000
#define MM_ADDR_IO_TSC 0x80016000
#define MM_ADDR_IO_TMR 0x80017000
#define MM_ADDR_IO_WATCHDOG 0x80017800
#define MM_ADDR_IO_ETM 0x80018000
#define MM_ADDR_IO_DDRC 0x80019000
#define MM_ADDR_IO_SINTC 0x80100000
#define MM_ADDR_IO_INTC0 0x80200000
#define MM_ADDR_IO_INTC1 0x80201000
#define MM_ADDR_IO_GE 0x80300000
#define MM_ADDR_IO_USB_CTLR0 0x80400000
#define MM_ADDR_IO_USB_CTLR1 0x80410000
#define MM_ADDR_IO_USB_PHY 0x80420000
#define MM_ADDR_IO_SDIOH0 0x80500000
#define MM_ADDR_IO_SDIOH1 0x80600000
#define MM_ADDR_IO_VDEC 0x80700000
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* _MM_ADDR_H */
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file mm_io.h
*
* @brief Memory Map I/O definitions
*
* @note
* None
*/
/****************************************************************************/
#ifndef _MM_IO_H
#define _MM_IO_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/mm_addr.h>
#if !defined(CSP_SIMULATION)
#include <cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
#if defined(CONFIG_MMU)
/* This macro is referenced in <mach/io.h>
* Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
* This macro is referenced in <asm/arch/io.h>
*
* Assume VPM address is the last x MB of memory. For VPM, map to
* 0xf0000000 and up.
*/
#ifndef MM_IO_PHYS_TO_VIRT
#ifdef __ASSEMBLY__
#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
#else
#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
#endif
#endif
/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
#ifndef MM_IO_VIRT_TO_PHYS
#ifdef __ASSEMBLY__
#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
#else
#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
#endif
#endif
#else
#ifndef MM_IO_PHYS_TO_VIRT
#define MM_IO_PHYS_TO_VIRT(phys) (phys)
#endif
#ifndef MM_IO_VIRT_TO_PHYS
#define MM_IO_VIRT_TO_PHYS(virt) (virt)
#endif
#endif
/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* _MM_IO_H */
/*****************************************************************************
* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <cfg_global.h>
/*
* Physical vs virtual RAM address space conversion. These are
* private definitions which should NOT be used outside memory.h
* files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
*/
#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE
/*
* Maximum DMA memory allowed is 14M
*/
#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
#endif
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef MEMORY_SETTINGS_H
#define MEMORY_SETTINGS_H
/* ---- Include Files ---------------------------------------- */
/* ---- Constants and Types ---------------------------------- */
/* Memory devices */
/* NAND Flash timing for 166 MHz setting */
#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
| HW_CFG_NAND_tWP \
| HW_CFG_NAND_tWR \
| HW_CFG_NAND_tAS \
| HW_CFG_NAND_tOE \
| HW_CFG_NAND_tRC)
/* NOR Flash timing for 166 MHz setting */
#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
| HW_CFG_NOR_TBTA \
| HW_CFG_NOR_TWP \
| HW_CFG_NOR_TWR \
| HW_CFG_NOR_TAS \
| HW_CFG_NOR_TOE \
| HW_CFG_NOR_TRC_TLC)
#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
/* SDRAM Settings */
/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
/* ---- Variable Externs ------------------------------------- */
/* ---- Function Prototypes ---------------------------------- */
#endif /* MEMORY_SETTINGS_H */
/*
*
* Copyright (C) 2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Move VMALLOC_END to 0xf0000000 so that the vm space can range from
* 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
* larger physical memory designs better.
*/
#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/platform_device.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
#define IO_DESC(va, sz) { .virtual = va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_DEVICE }
#define MEM_DESC(va, sz) { .virtual = va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_MEMORY }
static struct map_desc bcmring_io_desc[] __initdata = {
IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */
IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */
IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */
MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */
IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */
};
void __init bcmring_map_io(void)
{
iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
}
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