Commit 66151bbd authored by Yoichi Yuasa's avatar Yoichi Yuasa Committed by Ralf Baechle
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[MIPS] vr41xx: Move IRQ numbers to asm-mips/vr41xx/irq.h


Signed-off-by: default avatarYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5fd32657
......@@ -21,7 +21,6 @@
#include <linux/pci.h>
#include <asm/vr41xx/mpc30x.h>
#include <asm/vr41xx/vrc4173.h>
static const int internal_func_irqs[] __initdata = {
VRC4173_CASCADE_IRQ,
......
......@@ -38,6 +38,7 @@
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/vr41xx.h>
static void __iomem *icu1_base;
......
......@@ -24,6 +24,7 @@
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/vr41xx.h>
#define IO_MEM_RESOURCE_START 0UL
......
......@@ -22,7 +22,7 @@
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
typedef struct irq_cascade {
int (*get_irq)(unsigned int, struct pt_regs *);
......
......@@ -28,6 +28,7 @@
#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/vrc4173.h>
......
......@@ -33,6 +33,7 @@
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/vr41xx/giu.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/vr41xx.h>
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
......
......@@ -30,7 +30,7 @@
#include <asm/div64.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
......
......@@ -38,6 +38,7 @@
#include <linux/tty_flip.h>
#include <asm/io.h>
#include <asm/vr41xx/irq.h>
#include <asm/vr41xx/siu.h>
#include <asm/vr41xx/vr41xx.h>
......
......@@ -20,7 +20,7 @@
#ifndef __ZAO_CAPCELLA_H
#define __ZAO_CAPCELLA_H
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
......@@ -15,8 +15,7 @@
#ifndef __NEC_CMBVR4133_H
#define __NEC_CMBVR4133_H
#include <asm/addrspace.h>
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
/*
* include/asm-mips/vr41xx/irq.h
*
* Interrupt numbers for NEC VR4100 series.
*
* Copyright (C) 1999 Michael Klar
* Copyright (C) 2001, 2002 Paul Mundt
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2002 TimeSys Corp.
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __NEC_VR41XX_IRQ_H
#define __NEC_VR41XX_IRQ_H
/*
* CPU core Interrupt Numbers
*/
#define MIPS_CPU_IRQ_BASE 0
#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
#define INT0_IRQ MIPS_CPU_IRQ(2)
#define INT1_IRQ MIPS_CPU_IRQ(3)
#define INT2_IRQ MIPS_CPU_IRQ(4)
#define INT3_IRQ MIPS_CPU_IRQ(5)
#define INT4_IRQ MIPS_CPU_IRQ(6)
#define TIMER_IRQ MIPS_CPU_IRQ(7)
/*
* SYINT1 Interrupt Numbers
*/
#define SYSINT1_IRQ_BASE 8
#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
#define BATTRY_IRQ SYSINT1_IRQ(0)
#define POWER_IRQ SYSINT1_IRQ(1)
#define RTCLONG1_IRQ SYSINT1_IRQ(2)
#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
/* RFU */
#define PIU_IRQ SYSINT1_IRQ(5)
#define AIU_IRQ SYSINT1_IRQ(6)
#define KIU_IRQ SYSINT1_IRQ(7)
#define GIUINT_IRQ SYSINT1_IRQ(8)
#define SIU_IRQ SYSINT1_IRQ(9)
#define BUSERR_IRQ SYSINT1_IRQ(10)
#define SOFTINT_IRQ SYSINT1_IRQ(11)
#define CLKRUN_IRQ SYSINT1_IRQ(12)
#define DOZEPIU_IRQ SYSINT1_IRQ(13)
#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
/*
* SYSINT2 Interrupt Numbers
*/
#define SYSINT2_IRQ_BASE 24
#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
#define RTCLONG2_IRQ SYSINT2_IRQ(0)
#define LED_IRQ SYSINT2_IRQ(1)
#define HSP_IRQ SYSINT2_IRQ(2)
#define TCLOCK_IRQ SYSINT2_IRQ(3)
#define FIR_IRQ SYSINT2_IRQ(4)
#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
#define DSIU_IRQ SYSINT2_IRQ(5)
#define PCI_IRQ SYSINT2_IRQ(6)
#define SCU_IRQ SYSINT2_IRQ(7)
#define CSI_IRQ SYSINT2_IRQ(8)
#define BCU_IRQ SYSINT2_IRQ(9)
#define ETHERNET_IRQ SYSINT2_IRQ(10)
#define SYSINT2_IRQ_LAST ETHERNET_IRQ
/*
* GIU Interrupt Numbers
*/
#define GIU_IRQ_BASE 40
#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
#define GIU_IRQ_LAST GIU_IRQ(31)
/*
* VRC4173 Interrupt Numbers
*/
#define VRC4173_IRQ_BASE 72
#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
#define VRC4173_USB_IRQ VRC4173_IRQ(0)
#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
/* RFU */
#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
#endif /* __NEC_VR41XX_IRQ_H */
......@@ -20,7 +20,7 @@
#ifndef __VICTOR_MPC30X_H
#define __VICTOR_MPC30X_H
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
......@@ -23,7 +23,7 @@
#ifndef __TANBAC_TB0219_H
#define __TANBAC_TB0219_H
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
......@@ -20,7 +20,7 @@
#ifndef __TANBAC_TB0226_H
#define __TANBAC_TB0226_H
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
......@@ -22,7 +22,7 @@
#ifndef __TANBAC_TB0287_H
#define __TANBAC_TB0287_H
#include <asm/vr41xx/vr41xx.h>
#include <asm/vr41xx/irq.h>
/*
* General-Purpose I/O Pin Number
......
......@@ -74,59 +74,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
/*
* Interrupt Control Unit
*/
/* CPU core Interrupt Numbers */
#define MIPS_CPU_IRQ_BASE 0
#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
#define INT0_IRQ MIPS_CPU_IRQ(2)
#define INT1_IRQ MIPS_CPU_IRQ(3)
#define INT2_IRQ MIPS_CPU_IRQ(4)
#define INT3_IRQ MIPS_CPU_IRQ(5)
#define INT4_IRQ MIPS_CPU_IRQ(6)
#define TIMER_IRQ MIPS_CPU_IRQ(7)
/* SYINT1 Interrupt Numbers */
#define SYSINT1_IRQ_BASE 8
#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
#define BATTRY_IRQ SYSINT1_IRQ(0)
#define POWER_IRQ SYSINT1_IRQ(1)
#define RTCLONG1_IRQ SYSINT1_IRQ(2)
#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
/* RFU */
#define PIU_IRQ SYSINT1_IRQ(5)
#define AIU_IRQ SYSINT1_IRQ(6)
#define KIU_IRQ SYSINT1_IRQ(7)
#define GIUINT_IRQ SYSINT1_IRQ(8)
#define SIU_IRQ SYSINT1_IRQ(9)
#define BUSERR_IRQ SYSINT1_IRQ(10)
#define SOFTINT_IRQ SYSINT1_IRQ(11)
#define CLKRUN_IRQ SYSINT1_IRQ(12)
#define DOZEPIU_IRQ SYSINT1_IRQ(13)
#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
/* SYSINT2 Interrupt Numbers */
#define SYSINT2_IRQ_BASE 24
#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
#define RTCLONG2_IRQ SYSINT2_IRQ(0)
#define LED_IRQ SYSINT2_IRQ(1)
#define HSP_IRQ SYSINT2_IRQ(2)
#define TCLOCK_IRQ SYSINT2_IRQ(3)
#define FIR_IRQ SYSINT2_IRQ(4)
#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
#define DSIU_IRQ SYSINT2_IRQ(5)
#define PCI_IRQ SYSINT2_IRQ(6)
#define SCU_IRQ SYSINT2_IRQ(7)
#define CSI_IRQ SYSINT2_IRQ(8)
#define BCU_IRQ SYSINT2_IRQ(9)
#define ETHERNET_IRQ SYSINT2_IRQ(10)
#define SYSINT2_IRQ_LAST ETHERNET_IRQ
/* GIU Interrupt Numbers */
#define GIU_IRQ_BASE 40
#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
#define GIU_IRQ_LAST GIU_IRQ(31)
extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
......
......@@ -26,26 +26,6 @@
#include <asm/io.h>
/*
* Interrupt Number
*/
#define VRC4173_IRQ_BASE 72
#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
#define VRC4173_USB_IRQ VRC4173_IRQ(0)
#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
/* RFU */
#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
/*
* PCI I/O accesses
*/
......
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