Commit 63a75b91 authored by Senthil Balasubramanian's avatar Senthil Balasubramanian Committed by John W. Linville

ath9k: Reduce PLL Settle time and eliminate redundant PLL calls.

Reduce PLL Settle time and eliminate redundant PLL calls. Also reduce
the LoadNF timeout from 10 msec to 250usec as the 10 msec timeout was
hit with AR9285 in some cases.
Signed-off-by: default avatarSenthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 1d50a69b
...@@ -653,11 +653,11 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -653,11 +653,11 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
AR_PHY_AGC_CONTROL_NO_UPDATE_NF); AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
for (j = 0; j < 1000; j++) { for (j = 0; j < 5; j++) {
if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
AR_PHY_AGC_CONTROL_NF) == 0) AR_PHY_AGC_CONTROL_NF) == 0)
break; break;
udelay(10); udelay(50);
} }
for (i = 0; i < NUM_NF_READINGS; i++) { for (i = 0; i < NUM_NF_READINGS; i++) {
......
...@@ -1691,8 +1691,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) ...@@ -1691,8 +1691,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
if (!AR_SREV_9100(ah)) if (!AR_SREV_9100(ah))
REG_WRITE(ah, AR_RC, 0); REG_WRITE(ah, AR_RC, 0);
ath9k_hw_init_pll(ah, NULL);
if (AR_SREV_9100(ah)) if (AR_SREV_9100(ah))
udelay(50); udelay(50);
...@@ -2885,6 +2883,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) ...@@ -2885,6 +2883,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
ATH9K_RESET_POWER_ON) != true) { ATH9K_RESET_POWER_ON) != true) {
return false; return false;
} }
ath9k_hw_init_pll(ah, NULL);
} }
if (AR_SREV_9100(ah)) if (AR_SREV_9100(ah))
REG_SET_BIT(ah, AR_RTC_RESET, REG_SET_BIT(ah, AR_RTC_RESET,
...@@ -3968,7 +3967,11 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) ...@@ -3968,7 +3967,11 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
bool ath9k_hw_phy_disable(struct ath_hw *ah) bool ath9k_hw_phy_disable(struct ath_hw *ah)
{ {
return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
return false;
ath9k_hw_init_pll(ah, NULL);
return true;
} }
bool ath9k_hw_disable(struct ath_hw *ah) bool ath9k_hw_disable(struct ath_hw *ah)
...@@ -3976,7 +3979,11 @@ bool ath9k_hw_disable(struct ath_hw *ah) ...@@ -3976,7 +3979,11 @@ bool ath9k_hw_disable(struct ath_hw *ah)
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
return false; return false;
return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
return false;
ath9k_hw_init_pll(ah, NULL);
return true;
} }
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
......
...@@ -102,7 +102,7 @@ ...@@ -102,7 +102,7 @@
#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
#define BASE_ACTIVATE_DELAY 100 #define BASE_ACTIVATE_DELAY 100
#define RTC_PLL_SETTLE_DELAY 1000 #define RTC_PLL_SETTLE_DELAY 100
#define COEF_SCALE_S 24 #define COEF_SCALE_S 24
#define HT40_CHANNEL_CENTER_SHIFT 10 #define HT40_CHANNEL_CENTER_SHIFT 10
......
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