Commit 60b67f51 authored by Sujith's avatar Sujith Committed by John W. Linville
Browse files

ath9k: Cleanup data structures related to HW capabilities


Signed-off-by: default avatarSujith Manoharan <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent b08cbcd4
......@@ -147,94 +147,95 @@ struct ath_desc {
#define ATH9K_RXDESC_INTREQ 0x0020
enum hal_capability_type {
HAL_CAP_CIPHER = 0,
HAL_CAP_TKIP_MIC,
HAL_CAP_TKIP_SPLIT,
HAL_CAP_PHYCOUNTERS,
HAL_CAP_DIVERSITY,
HAL_CAP_PSPOLL,
HAL_CAP_TXPOW,
HAL_CAP_PHYDIAG,
HAL_CAP_MCAST_KEYSRCH,
HAL_CAP_TSF_ADJUST,
HAL_CAP_WME_TKIPMIC,
HAL_CAP_RFSILENT,
HAL_CAP_ANT_CFG_2GHZ,
HAL_CAP_ANT_CFG_5GHZ
enum ath9k_hw_caps {
ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
ATH9K_HW_CAP_MIC_CKIP = BIT(2),
ATH9K_HW_CAP_MIC_TKIP = BIT(3),
ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
ATH9K_HW_CAP_VEOL = BIT(7),
ATH9K_HW_CAP_BSSIDMASK = BIT(8),
ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
ATH9K_HW_CAP_HT = BIT(12),
ATH9K_HW_CAP_GTT = BIT(13),
ATH9K_HW_CAP_FASTCC = BIT(14),
ATH9K_HW_CAP_RFSILENT = BIT(15),
ATH9K_HW_CAP_WOW = BIT(16),
ATH9K_HW_CAP_CST = BIT(17),
ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
};
struct hal_capabilities {
u32 halChanSpreadSupport:1,
halChapTuningSupport:1,
halMicAesCcmSupport:1,
halMicCkipSupport:1,
halMicTkipSupport:1,
halCipherAesCcmSupport:1,
halCipherCkipSupport:1,
halCipherTkipSupport:1,
halVEOLSupport:1,
halBssIdMaskSupport:1,
halMcastKeySrchSupport:1,
halTsfAddSupport:1,
halChanHalfRate:1,
halChanQuarterRate:1,
halHTSupport:1,
halGTTSupport:1,
halFastCCSupport:1,
halRfSilentSupport:1,
halWowSupport:1,
halCSTSupport:1,
halEnhancedPmSupport:1,
halAutoSleepSupport:1,
hal4kbSplitTransSupport:1,
halWowMatchPatternExact:1;
u32 halWirelessModes;
u16 halTotalQueues;
u16 halKeyCacheSize;
u16 halLow5GhzChan, halHigh5GhzChan;
u16 halLow2GhzChan, halHigh2GhzChan;
u16 halNumMRRetries;
u16 halRtsAggrLimit;
u8 halTxChainMask;
u8 halRxChainMask;
u16 halTxTrigLevelMax;
u16 halRegCap;
u8 halNumGpioPins;
u8 halNumAntCfg2GHz;
u8 halNumAntCfg5GHz;
enum ath9k_capability_type {
ATH9K_CAP_CIPHER = 0,
ATH9K_CAP_TKIP_MIC,
ATH9K_CAP_TKIP_SPLIT,
ATH9K_CAP_PHYCOUNTERS,
ATH9K_CAP_DIVERSITY,
ATH9K_CAP_TXPOW,
ATH9K_CAP_PHYDIAG,
ATH9K_CAP_MCAST_KEYSRCH,
ATH9K_CAP_TSF_ADJUST,
ATH9K_CAP_WME_TKIPMIC,
ATH9K_CAP_RFSILENT,
ATH9K_CAP_ANT_CFG_2GHZ,
ATH9K_CAP_ANT_CFG_5GHZ
};
struct hal_ops_config {
int ath_hal_dma_beacon_response_time;
int ath_hal_sw_beacon_response_time;
int ath_hal_additional_swba_backoff;
int ath_hal_6mb_ack;
int ath_hal_cwmIgnoreExtCCA;
u8 ath_hal_pciePowerSaveEnable;
u8 ath_hal_pcieL1SKPEnable;
u8 ath_hal_pcieClockReq;
u32 ath_hal_pcieWaen;
int ath_hal_pciePowerReset;
u8 ath_hal_pcieRestore;
u8 ath_hal_analogShiftReg;
u8 ath_hal_htEnable;
u32 ath_hal_ofdmTrigLow;
u32 ath_hal_ofdmTrigHigh;
u32 ath_hal_cckTrigHigh;
u32 ath_hal_cckTrigLow;
u32 ath_hal_enableANI;
u8 ath_hal_noiseImmunityLvl;
u32 ath_hal_ofdmWeakSigDet;
u32 ath_hal_cckWeakSigThr;
u8 ath_hal_spurImmunityLvl;
u8 ath_hal_firStepLvl;
int8_t ath_hal_rssiThrHigh;
int8_t ath_hal_rssiThrLow;
u16 ath_hal_diversityControl;
u16 ath_hal_antennaSwitchSwap;
int ath_hal_serializeRegMode;
int ath_hal_intrMitigation;
struct ath9k_hw_capabilities {
u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
u32 wireless_modes;
u16 total_queues;
u16 keycache_size;
u16 low_5ghz_chan, high_5ghz_chan;
u16 low_2ghz_chan, high_2ghz_chan;
u16 num_mr_retries;
u16 rts_aggr_limit;
u8 tx_chainmask;
u8 rx_chainmask;
u16 tx_triglevel_max;
u16 reg_cap;
u8 num_gpio_pins;
u8 num_antcfg_2ghz;
u8 num_antcfg_5ghz;
};
struct ath9k_ops_config {
int dma_beacon_response_time;
int sw_beacon_response_time;
int additional_swba_backoff;
int ack_6mb;
int cwm_ignore_extcca;
u8 pcie_powersave_enable;
u8 pcie_l1skp_enable;
u8 pcie_clock_req;
u32 pcie_waen;
int pcie_power_reset;
u8 pcie_restore;
u8 analog_shiftreg;
u8 ht_enable;
u32 ofdm_trig_low;
u32 ofdm_trig_high;
u32 cck_trig_high;
u32 cck_trig_low;
u32 enable_ani;
u8 noise_immunity_level;
u32 ofdm_weaksignal_det;
u32 cck_weaksignal_thr;
u8 spur_immunity_level;
u8 firstep_level;
int8_t rssi_thr_high;
int8_t rssi_thr_low;
u16 diversity_control;
u16 antenna_switch_swap;
int serialize_regmode;
int intr_mitigation;
#define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2
......@@ -246,8 +247,8 @@ struct hal_ops_config {
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
int ath_hal_spurMode;
u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
int spurmode;
u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
};
enum ath9k_tx_queue {
......@@ -815,8 +816,8 @@ struct ath_hal {
u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
u32 ah_flags;
enum ath9k_opmode ah_opmode;
struct hal_ops_config ah_config;
struct hal_capabilities ah_caps;
struct ath9k_ops_config ah_config;
struct ath9k_hw_capabilities ah_caps;
int16_t ah_powerLimit;
u16 ah_maxPowerLevel;
u32 ah_tpScale;
......@@ -878,7 +879,7 @@ struct chan_centers {
};
int ath_hal_getcapability(struct ath_hal *ah,
enum hal_capability_type type,
enum ath9k_capability_type type,
u32 capability,
u32 *result);
const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
......@@ -947,11 +948,11 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
bool ath9k_hw_phycounters(struct ath_hal *ah);
bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
bool ath9k_hw_getcapability(struct ath_hal *ah,
enum hal_capability_type type,
enum ath9k_capability_type type,
u32 capability,
u32 *result);
bool ath9k_hw_setcapability(struct ath_hal *ah,
enum hal_capability_type type,
enum ath9k_capability_type type,
u32 capability,
u32 setting,
int *status);
......
......@@ -85,7 +85,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
flags = ATH9K_TXDESC_NOACK;
if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) {
if (sc->sc_opmode == ATH9K_M_IBSS &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
ds->ds_link = bf->bf_daddr; /* self-linked */
flags |= ATH9K_TXDESC_VEOL;
/* Let hardware handle antenna switching. */
......@@ -375,7 +376,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
list_del(&avp->av_bcbuf->list);
if (sc->sc_opmode == ATH9K_M_HOSTAP ||
!sc->sc_ah->ah_caps.halVEOLSupport) {
!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
int slot;
/*
* Assign the vap to a beacon xmit slot. As
......@@ -939,7 +940,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* deal with things.
*/
intval |= ATH9K_BEACON_ENA;
if (!ah->ah_caps.halVEOLSupport)
if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
sc->sc_imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc);
} else if (sc->sc_opmode == ATH9K_M_HOSTAP) {
......@@ -958,7 +959,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* When using a self-linked beacon descriptor in
* ibss mode load it once here.
*/
if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport)
if (sc->sc_opmode == ATH9K_M_IBSS &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
ath_beacon_start_adhoc(sc, 0);
}
#undef TSF_TO_TU
......
......@@ -536,7 +536,7 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
* sc_chainmask_auto_sel is used for internal global auto-switching
* enabled/disabled setting
*/
if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) {
if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
cm->cur_tx_mask = sc->sc_tx_chainmask;
return cm->cur_tx_mask;
}
......@@ -580,8 +580,8 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
{
sc->sc_update_chainmask = 1;
if (is_ht) {
sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask;
sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
} else {
sc->sc_tx_chainmask = 1;
sc->sc_rx_chainmask = 1;
......@@ -780,8 +780,8 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
ath_stop(sc);
/* Initialize chanmask selection */
sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
/* Reset SERDES registers */
ath9k_hw_configpcipowersave(ah, 0);
......@@ -832,10 +832,10 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
| ATH9K_INT_RXEOL | ATH9K_INT_RXORN
| ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
if (ah->ah_caps.halGTTSupport)
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
sc->sc_imask |= ATH9K_INT_GTT;
if (ah->ah_caps.halHTSupport)
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
sc->sc_imask |= ATH9K_INT_CST;
/*
......@@ -851,8 +851,9 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
* that does, if not overridden by configuration,
* enable the TIM interrupt when operating as station.
*/
if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA &&
!sc->sc_config.swBeaconProcess)
if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
(sc->sc_opmode == ATH9K_M_STA) &&
!sc->sc_config.swBeaconProcess)
sc->sc_imask |= ATH9K_INT_TIM;
/*
* Don't enable interrupts here as we've not yet built our
......@@ -1061,7 +1062,8 @@ irqreturn_t ath_isr(int irq, void *dev)
ath9k_hw_set_interrupts(ah, sc->sc_imask);
}
if (status & ATH9K_INT_TIM_TIMER) {
if (!ah->ah_caps.halAutoSleepSupport) {
if (!(ah->ah_caps.hw_caps &
ATH9K_HW_CAP_AUTOSLEEP)) {
/* Clear RxAbort bit so that we can
* receive frames */
ath9k_hw_setrxabort(ah, 0);
......@@ -1166,10 +1168,10 @@ int ath_init(u16 devid, struct ath_softc *sc)
sc->sc_ah = ah;
/* Get the chipset-specific aggr limit. */
sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit;
/* Get the hardware key cache size. */
sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
sc->sc_keymax = ah->ah_caps.keycache_size;
if (sc->sc_keymax > ATH_KEYMAX) {
DPRINTF(sc, ATH_DBG_KEYCACHE,
"%s: Warning, using only %u entries in %u key cache\n",
......@@ -1284,7 +1286,7 @@ int ath_init(u16 devid, struct ath_softc *sc)
goto bad2;
}
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
ATH9K_CIPHER_TKIP, NULL)) {
/*
* Whether we should enable h/w TKIP MIC.
......@@ -1292,7 +1294,8 @@ int ath_init(u16 devid, struct ath_softc *sc)
* report WMM capable, so it's always safe to turn on
* TKIP MIC in this case.
*/
ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL);
ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
0, 1, NULL);
}
/*
......@@ -1301,30 +1304,30 @@ int ath_init(u16 devid, struct ath_softc *sc)
* With split mic keys the number of stations is limited
* to 27 otherwise 59.
*/
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
ATH9K_CIPHER_TKIP, NULL)
&& ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
&& ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
ATH9K_CIPHER_MIC, NULL)
&& ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT,
&& ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
0, NULL))
sc->sc_splitmic = 1;
/* turn on mcast key search if possible */
if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL))
(void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
(void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1, NULL);
sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
sc->sc_config.txpowlimit_override = 0;
/* 11n Capabilities */
if (ah->ah_caps.halHTSupport) {
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
sc->sc_txaggr = 1;
sc->sc_rxaggr = 1;
}
sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
/* Configuration for rx chain detection */
sc->sc_rxchaindetect_ref = 0;
......@@ -1333,11 +1336,11 @@ int ath_init(u16 devid, struct ath_softc *sc)
sc->sc_rxchaindetect_delta5GHz = 30;
sc->sc_rxchaindetect_delta2GHz = 30;
ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
sc->sc_defant = ath9k_hw_getdefantenna(ah);
ath9k_hw_getmac(ah, sc->sc_myaddr);
if (ah->ah_caps.halBssIdMaskSupport) {
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
......@@ -1555,7 +1558,7 @@ void ath_update_txpow(struct ath_softc *sc)
if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
/* read back in case value is clamped */
ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 1, &txpow);
ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
sc->sc_curtxpow = txpow;
}
}
......@@ -1757,7 +1760,7 @@ int ath_descdma_setup(struct ath_softc *sc,
* descriptors that cross the 4K page boundary. Assume
* one skipped descriptor per 4K page.
*/
if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
u32 ndesc_skipped =
ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
u32 dma_len;
......@@ -1798,7 +1801,8 @@ int ath_descdma_setup(struct ath_softc *sc,
bf->bf_desc = ds;
bf->bf_daddr = DS2PHYS(dd, ds);
if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
if (!(sc->sc_ah->ah_caps.hw_caps &
ATH9K_HW_CAP_4KB_SPLITTRANS)) {
/*
* Skip descriptor addresses which can cause 4KB
* boundary crossing (addr + length) with a 32 dword
......
This diff is collapsed.
......@@ -1268,14 +1268,14 @@ static int ath_attach(u16 devid,
sc->rates[IEEE80211_BAND_2GHZ];
sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
if (sc->sc_ah->ah_caps.halHTSupport)
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
/* Setup HT capabilities for 2.4Ghz*/
setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
&sc->sbands[IEEE80211_BAND_2GHZ];
if (sc->sc_ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) {
if (sc->sc_ah->ah_caps.wireless_modes & ATH9K_MODE_SEL_11A) {
sc->sbands[IEEE80211_BAND_5GHZ].channels =
sc->channels[IEEE80211_BAND_5GHZ];
sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
......@@ -1283,7 +1283,7 @@ static int ath_attach(u16 devid,
sc->sbands[IEEE80211_BAND_5GHZ].band =
IEEE80211_BAND_5GHZ;
if (sc->sc_ah->ah_caps.halHTSupport)
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
/* Setup HT capabilities for 5Ghz*/
setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
......
......@@ -780,7 +780,7 @@ struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah)
ar5416_attach_ratetables(asc);
/* Save Maximum TX Trigger Level (used for 11n) */
tx_triglevel_max = ah->ah_caps.halTxTrigLevelMax;
tx_triglevel_max = ah->ah_caps.tx_triglevel_max;
/* return alias for ath_rate_softc * */
return asc;
}
......
......@@ -478,7 +478,7 @@ static void ath_opmode_init(struct ath_softc *sc)
ath9k_hw_setrxfilter(ah, rfilt);
/* configure bssid mask */
if (ah->ah_caps.halBssIdMaskSupport)
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
/* configure operational mode */
......@@ -1018,7 +1018,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
PCI_DMA_FROMDEVICE);
/* XXX: Ah! make me more readable, use a helper */
if (ah->ah_caps.halHTSupport) {
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
if (ds->ds_rxstat.rs_moreaggr == 0) {
rx_status.rssictl[0] =
ds->ds_rxstat.rs_rssi_ctl0;
......
......@@ -87,7 +87,7 @@ static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
{
u32 regcap;
regcap = ah->ah_caps.halRegCap;
regcap = ah->ah_caps.reg_cap;
if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND)
return true;
......@@ -138,7 +138,7 @@ ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
{
u32 modesAvail;
modesAvail = ah->ah_caps.halWirelessModes;
modesAvail = ah->ah_caps.wireless_modes;
if ((modesAvail & ATH9K_MODE_SEL_11G) && (!country->allow11g))
modesAvail &= ~ATH9K_MODE_SEL_11G;
......@@ -436,7 +436,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
return false;
}
if ((fband->channelBW == CHANNEL_HALF_BW) &&
!ah->ah_caps.halChanHalfRate) {
!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Skipping %u half rate channel\n",
__func__, c);
......@@ -444,7 +444,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
}
if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
!ah->ah_caps.halChanQuarterRate) {
!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) {
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
"%s: Skipping %u quarter rate channel\n",
__func__, c);
......@@ -529,7 +529,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
if ((c < 2412) || (c > 2462)) {
if (rd5GHz.regDmnEnum == MKK1 ||
rd5GHz.regDmnEnum == MKK2) {
u32 regcap = ah->ah_caps.halRegCap;
u32 regcap = ah->ah_caps.reg_cap;
if (!(regcap &
(AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
AR_EEPROM_EEREGCAP_EN_KK_U2 |
......@@ -594,7 +594,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
if (j_bandcheck[i].freqbandbit == b) {
regcap = ah->ah_caps.halRegCap;
regcap = ah->ah_caps.reg_cap;
if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) {
skipband = true;
} else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) ||
......@@ -726,7 +726,7 @@ ath9k_regd_init_channels(struct ath_hal *ah,
}
if (country == NULL) {
modesAvail = ah->ah_caps.halWirelessModes;
modesAvail = ah->ah_caps.wireless_modes;
} else {
modesAvail = ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz);
if (!enableOutdoor)
......
......@@ -781,7 +781,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
* let rate series flags determine which rates will actually
* use RTS.
*/
if (ah->ah_caps.halHTSupport && bf->bf_isdata) {
if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf->bf_isdata) {
BUG_ON(!an);
/*
* 802.11g protection not needed, use our default behavior
......@@ -897,7 +897,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
* For non-HT devices, calculate RTS/CTS duration in software
* and disable multi-rate retry.
*/
if (flags && !ah->ah_caps.halHTSupport) {
if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
/*
* Compute the transmit duration based on the frame
* size and the size of an ACK frame. We call into the
......
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