Commit 60a0e5d9 authored by Santosh Shilimkar's avatar Santosh Shilimkar Committed by Paul Walmsley
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OMAP4: clock data: Keep L3INSTR clock domain modulemode under HW control



L3INSTR clock domain is read only register and its reset value is
HW_AUTO. The modules withing this clock domain needs to be kept under
hardware control.

MODULEMODE:
- 0x0: Module is disable by software. Any INTRCONN access to module
  results in an error, except if resulting from a module wakeup
  (asynchronous wakeup).
- 0x1: Module is managed automatically by hardware according to
  clock domain transition. A clock domain sleep transition put
  module into idle. A wakeup domain transition put it back
  into function. If CLKTRCTRL=3, any INTRCONN access to module
  is always granted. Module clocks may be gated according to
  the clock domain state.

This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL
and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control
by using ENABLE_ON_INIT flag.

Without this the OMAP4 device OFF mode SAR restore phase aborts during
interconnect register restore phase. This can be also handled by doing
explicit a clock enable and disable in the low power code since there
is no direct module associated with it. But that seems not necessary
since the clock domain is under HW control.
Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarBenoit Cousson <b-cousson@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 80f09365
......@@ -1829,6 +1829,7 @@ static struct clk l3_instr_ick = {
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
......@@ -1839,6 +1840,7 @@ static struct clk l3_main_3_ick = {
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
......@@ -2143,6 +2145,7 @@ static struct clk ocp_wp_noc_ick = {
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
......
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