Commit 5df3f0ea authored by dave graham's avatar dave graham Committed by David S. Miller
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e1000e: Disable dynamic clock gating for 82571 per si errata.



82571 and 82572 Errata #13 documents that the Si feature DMA Dynamic
Clock Gating should be disabled, and identifies the workaround of
disabling the feature by EEPROM setting. EEPROM versions that do not
include the recommended workaround have been found in the field, and so
some customers remain at risk. Because the feature DMA Dynamic clock
Gating can be disabled by directly setting the appropriate bit in the
E1000_CTRL_EXT register, this patch overrides the EEPROM setting, and
force-disables the feature.
Signed-off-by: default avatardave graham <david.graham@intel.com>
Acked-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 111b9dc5
...@@ -980,6 +980,18 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) ...@@ -980,6 +980,18 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
reg |= E1000_PBA_ECC_CORR_EN; reg |= E1000_PBA_ECC_CORR_EN;
ew32(PBA_ECC, reg); ew32(PBA_ECC, reg);
} }
/*
* Workaround for hardware errata.
* Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
*/
if ((hw->mac.type == e1000_82571) ||
(hw->mac.type == e1000_82572)) {
reg = er32(CTRL_EXT);
reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
ew32(CTRL_EXT, reg);
}
/* PCI-Ex Control Registers */ /* PCI-Ex Control Registers */
if (hw->mac.type == e1000_82574) { if (hw->mac.type == e1000_82574) {
......
...@@ -69,6 +69,7 @@ ...@@ -69,6 +69,7 @@
#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
#define E1000_CTRL_EXT_EIAME 0x01000000 #define E1000_CTRL_EXT_EIAME 0x01000000
......
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