Commit 58a6d451 authored by Ricardo Mendoza's avatar Ricardo Mendoza Committed by Ralf Baechle
Browse files

MIPS: RM7000: Make use of cache_op() instead of inline asm

Small cleanup of the cache code to get rid of inline asm, in preparation
to give tertiary cache support.
Signed-off-by: default avatarRicardo Mendoza <>

Signed-off-by: default avatarRalf Baechle <>
parent 65ab2826
...@@ -95,16 +95,8 @@ static __cpuinit void __rm7k_sc_enable(void) ...@@ -95,16 +95,8 @@ static __cpuinit void __rm7k_sc_enable(void)
write_c0_taglo(0); write_c0_taglo(0);
write_c0_taghi(0); write_c0_taghi(0);
for (i = 0; i < scache_size; i += sc_lsize) { for (i = 0; i < scache_size; i += sc_lsize)
__asm__ __volatile__ ( cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
".set noreorder\n\t"
".set mips3\n\t"
"cache %1, (%0)\n\t"
".set mips0\n\t"
".set reorder"
: "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
} }
static __cpuinit void rm7k_sc_enable(void) static __cpuinit void rm7k_sc_enable(void)
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