Commit 552d2f84 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] vpe: Add missing "space"
  [MIPS] Compliment va_start() with va_end().
  [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel
  [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259
  [MIPS] 64-bit Sibyte kernels need DMA32.
  [MIPS] Only build r4k clocksource for systems that work ok with it.
  [MIPS] Handle R4000/R4400 mfc0 from count register.
  [MIPS] Fix possible hang in LL/SC futex loops.
  [MIPS] Fix context DSP context / TLS pointer switching bug for new threads.
  [MIPS] IP32: More interrupt renumbering fixes.
  [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe.
  [MIPS] time: Fix negated condition in cevt-r4k driver.
  [MIPS] Fix pcspeaker build.
parents 09cfd929 b1e3afa0
......@@ -22,6 +22,7 @@ config MACH_ALCHEMY
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
......@@ -49,6 +50,7 @@ config BASLER_EXCITE_PROTOTYPE
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
......@@ -66,6 +68,7 @@ config BCM47XX
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
select CSRC_R4K
select CEVT_GT641XX
select DMA_NONCOHERENT
select HW_HAS_PCI
......@@ -85,6 +88,7 @@ config MACH_DECSTATION
bool "DECstations"
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select NO_IOPORT
select IRQ_CPU
......@@ -117,6 +121,7 @@ config MACH_JAZZ
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select CEVT_R4K
select CSRC_R4K
select GENERIC_ISA_DMA
select IRQ_CPU
select I8253
......@@ -137,6 +142,7 @@ config MACH_JAZZ
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
......@@ -154,6 +160,7 @@ config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
select ARCH_SPARSEMEM_ENABLE
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_LOONGSON2
select DMA_NONCOHERENT
select BOOT_ELF32
......@@ -179,6 +186,7 @@ config MIPS_ATLAS
bool "MIPS Atlas board"
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
......@@ -210,6 +218,7 @@ config MIPS_MALTA
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select IRQ_CPU
......@@ -241,6 +250,7 @@ config MIPS_MALTA
config MIPS_SEAD
bool "MIPS SEAD board"
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
......@@ -260,6 +270,7 @@ config MIPS_SEAD
config MIPS_SIM
bool 'MIPS simulator (MIPSsim)'
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
......@@ -278,6 +289,7 @@ config MIPS_SIM
config MARKEINS
bool "NEC EMMA2RH Mark-eins"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
......@@ -293,6 +305,7 @@ config MARKEINS
config MACH_VR41XX
bool "NEC VR4100 series based machines"
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
......@@ -330,6 +343,7 @@ config PMC_MSP
config PMC_YOSEMITE
bool "PMC-Sierra Yosemite eval board"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
......@@ -351,6 +365,7 @@ config PMC_YOSEMITE
config QEMU
bool "Qemu"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
......@@ -382,9 +397,11 @@ config SGI_IP22
select ARC32
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_EISA
select I8253
select I8259
select IP22_CPU_SCACHE
select IRQ_CPU
select GENERIC_ISA_DMA_SUPPORT_BROKEN
......@@ -427,6 +444,7 @@ config SGI_IP32
select ARC32
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
......@@ -498,6 +516,7 @@ config SIBYTE_SWARM
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
select ZONE_DMA32 if 64BIT
config SIBYTE_LITTLESUR
bool "Sibyte BCM91250C2-LittleSur"
......@@ -548,6 +567,7 @@ config SIBYTE_BIGSUR
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select ZONE_DMA32 if 64BIT
config SNI_RM
bool "SNI RM200/300/400"
......@@ -556,6 +576,7 @@ config SNI_RM
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HW_HAS_EISA
......@@ -599,6 +620,7 @@ config TOSHIBA_JMR3927
config TOSHIBA_RBTX4927
bool "Toshiba RBTX49[23]7 board"
select CEVT_R4K
select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
......@@ -621,6 +643,7 @@ config TOSHIBA_RBTX4927
config TOSHIBA_RBTX4938
bool "Toshiba RBTX4938 board"
select CEVT_R4K
select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
......@@ -642,6 +665,7 @@ config TOSHIBA_RBTX4938
config WR_PPMC
bool "Wind River PPMC board"
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select BOOT_ELF32
select DMA_NONCOHERENT
......@@ -752,6 +776,9 @@ config CEVT_TXX9
config CSRC_BCM1480
bool
config CSRC_R4K
bool
config CSRC_SB1250
bool
......@@ -1640,6 +1667,9 @@ config ARCH_DISCONTIGMEM_ENABLE
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
config ARCH_POPULATES_NODE_MAP
def_bool y
config ARCH_SPARSEMEM_ENABLE
bool
select SPARSEMEM_STATIC
......@@ -1945,6 +1975,9 @@ config I8253
config PCSPEAKER
bool
config ZONE_DMA32
bool
source "drivers/pcmcia/Kconfig"
source "drivers/pci/hotplug/Kconfig"
......
......@@ -138,6 +138,7 @@ config SOC_AU1X00
bool
select 64BIT_PHYS_ADDR
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
......
......@@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
......@@ -43,6 +44,7 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
obj-$(CONFIG_MIPS_MT) += mips-mt.o
obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
......
......@@ -219,7 +219,7 @@ static int c0_compare_int_usable(void)
return 1;
}
void __cpuinit mips_clockevent_init(void)
int __cpuinit mips_clockevent_init(void)
{
uint64_t mips_freq = mips_hpt_frequency;
unsigned int cpu = smp_processor_id();
......@@ -227,7 +227,7 @@ void __cpuinit mips_clockevent_init(void)
unsigned int irq;
if (!cpu_has_counter || !mips_hpt_frequency)
return;
return -ENXIO;
#ifdef CONFIG_MIPS_MT_SMTC
setup_smtc_dummy_clockevent_device();
......@@ -237,11 +237,11 @@ void __cpuinit mips_clockevent_init(void)
* device.
*/
if (cpu)
return;
return 0;
#endif
if (!c0_compare_int_usable())
return;
return -ENXIO;
/*
* With vectored interrupts things are getting platform specific.
......@@ -276,8 +276,8 @@ void __cpuinit mips_clockevent_init(void)
clockevents_register_device(cd);
if (!cp0_timer_irq_installed)
return;
if (cp0_timer_irq_installed)
return 0;
cp0_timer_irq_installed = 1;
......@@ -287,4 +287,6 @@ void __cpuinit mips_clockevent_init(void)
#else
setup_irq(irq, &c0_compare_irqaction);
#endif
return 0;
}
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 by Ralf Baechle
*/
static cycle_t c0_hpt_read(void)
{
return read_c0_count();
}
static struct clocksource clocksource_mips = {
.name = "MIPS",
.read = c0_hpt_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __init init_mips_clocksource(void)
{
/* Calclate a somewhat reasonable rating value */
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
clocksource_register(&clocksource_mips);
}
......@@ -269,7 +269,7 @@ static void __init bootmem_init(void)
static void __init bootmem_init(void)
{
unsigned long reserved_end;
unsigned long init_begin, reserved_end;
unsigned long mapstart = ~0UL;
unsigned long bootmap_size;
int i;
......@@ -342,6 +342,35 @@ static void __init bootmem_init(void)
*/
bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart,
min_low_pfn, max_low_pfn);
init_begin = PFN_UP(__pa_symbol(&__init_begin));
for (i = 0; i < boot_mem_map.nr_map; i++) {
unsigned long start, end;
start = PFN_UP(boot_mem_map.map[i].addr);
end = PFN_DOWN(boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size);
if (start <= init_begin)
start = init_begin;
if (start >= end)
continue;
#ifndef CONFIG_HIGHMEM
if (end > max_low_pfn)
end = max_low_pfn;
/*
* ... finally, is the area going away?
*/
if (end <= start)
continue;
#endif
add_active_range(0, start, end);
}
/*
* Register fully available low RAM pages with the bootmem allocator.
*/
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
*
* Symmetric Uniprocessor (TM) Support
*/
#include <linux/kernel.h>
#include <linux/sched.h>
/*
* Send inter-processor interrupt
*/
void up_send_ipi_single(int cpu, unsigned int action)
{
panic(KERN_ERR "%s called", __func__);
}
static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
{
panic(KERN_ERR "%s called", __func__);
}
/*
* After we've done initial boot, this function is called to allow the
* board code to clean up state, if needed
*/
void __cpuinit up_init_secondary(void)
{
}
void __cpuinit up_smp_finish(void)
{
}
/* Hook for after all CPUs are online */
void up_cpus_done(void)
{
}
/*
* Firmware CPU startup hook
*/
void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
{
}
void __init up_smp_setup(void)
{
}
void __init up_prepare_cpus(unsigned int max_cpus)
{
}
struct plat_smp_ops up_smp_ops = {
.send_ipi_single = up_send_ipi_single,
.send_ipi_mask = up_send_ipi_mask,
.init_secondary = up_init_secondary,
.smp_finish = up_smp_finish,
.cpus_done = up_cpus_done,
.boot_secondary = up_boot_secondary,
.smp_setup = up_smp_setup,
.prepare_cpus = up_prepare_cpus,
};
......@@ -50,14 +50,6 @@ int update_persistent_clock(struct timespec now)
return rtc_mips_set_mmss(now.tv_sec);
}
/*
* High precision timer functions for a R4k-compatible timer.
*/
static cycle_t c0_hpt_read(void)
{
return read_c0_count();
}
int (*mips_timer_state)(void);
int null_perf_irq(void)
......@@ -84,55 +76,6 @@ EXPORT_SYMBOL(perf_irq);
unsigned int mips_hpt_frequency;
static struct clocksource clocksource_mips = {
.name = "MIPS",
.read = c0_hpt_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static unsigned int __init calibrate_hpt(void)
{
cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
const int loops = HZ / 10;
int log_2_loops = 0;
int i;
/*
* We want to calibrate for 0.1s, but to avoid a 64-bit
* division we round the number of loops up to the nearest
* power of 2.
*/
while (loops > 1 << log_2_loops)
log_2_loops++;
i = 1 << log_2_loops;
/*
* Wait for a rising edge of the timer interrupt.
*/
while (mips_timer_state());
while (!mips_timer_state());
/*
* Now see how many high precision timer ticks happen
* during the calculated number of periods between timer
* interrupts.
*/
hpt_start = clocksource_mips.read();
do {
while (mips_timer_state());
while (!mips_timer_state());
} while (--i);
hpt_end = clocksource_mips.read();
hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
hz = HZ;
frequency = hpt_count * hz;
return frequency >> log_2_loops;
}
void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
{
u64 temp;
......@@ -166,16 +109,6 @@ void __cpuinit clockevent_set_clock(struct clock_event_device *cd,
cd->mult = (u32) temp;
}
static void __init init_mips_clocksource(void)
{
/* Calclate a somewhat reasonable rating value */
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
clocksource_register(&clocksource_mips);
}
void __init __weak plat_time_init(void)
{
}
......@@ -194,21 +127,42 @@ void __init plat_timer_setup(void)
BUG();
}
static __init int cpu_has_mfc0_count_bug(void)
{
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
/*
* V3.0 is documented as suffering from the mfc0 from count bug.
* Afaik this is the last version of the R4000. Later versions
* were marketed as R4400.
*/
return 1;
case CPU_R4400PC:
case CPU_R4400SC:
case CPU_R4400MC:
/*
* The published errata for the R4400 upto 3.0 say the CPU
* has the mfc0 from count bug.
*/
if ((current_cpu_data.processor_id & 0xff) <= 0x30)
return 1;
/*
* I don't have erratas for newer R4400 so be paranoid.
*/
return 1;
}
return 0;
}
void __init time_init(void)
{
plat_time_init();
if (cpu_has_counter && (mips_hpt_frequency || mips_timer_state)) {
/* We know counter frequency. Or we can get it. */
if (!mips_hpt_frequency)
mips_hpt_frequency = calibrate_hpt();
/* Report the high precision timer rate for a reference. */
printk("Using %u.%03u MHz high precision timer.\n",
((mips_hpt_frequency + 500) / 1000) / 1000,
((mips_hpt_frequency + 500) / 1000) % 1000);
if (mips_clockevent_init() || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}
mips_clockevent_init();
}
......@@ -470,7 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
*/
if (v != l->value) {
printk(KERN_DEBUG "VPE loader: "
"apply_r_mips_lo16/hi16: "
"apply_r_mips_lo16/hi16: \t"
"inconsistent value information\n");
return -ENOEXEC;
}
......@@ -629,7 +629,7 @@ static void simplify_symbols(Elf_Shdr * sechdrs,
break;
case SHN_MIPS_SCOMMON:
printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON"
printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON "
"symbol <%s> st_shndx %d\n", strtab + sym[i].st_name,
sym[i].st_shndx);
// .sbss section
......
......@@ -108,6 +108,7 @@ int ieee754si_xcpt(int r, const char *op, ...)
ax.rv.si = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.si;
}
......@@ -122,5 +123,6 @@ s64 ieee754di_xcpt(s64 r, const char *op, ...)
ax.rv.di = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.di;
}
......@@ -57,6 +57,7 @@ ieee754dp ieee754dp_xcpt(ieee754dp r, const char *op, ...)
ax.rv.dp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.dp;
}
......@@ -83,6 +84,7 @@ ieee754dp ieee754dp_nanxcpt(ieee754dp r, const char *op, ...)
ax.rv.dp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.dp;
}
......
......@@ -58,6 +58,7 @@ ieee754sp ieee754sp_xcpt(ieee754sp r, const char *op, ...)
ax.rv.sp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.sp;
}
......@@ -84,6 +85,7 @@ ieee754sp ieee754sp_nanxcpt(ieee754sp r, const char *op, ...)
ax.rv.sp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
va_end(ax.ap);
return ax.rv.sp;
}
......
......@@ -101,9 +101,7 @@ unsigned __init get_c0_compare_int(void)
void __init plat_time_init(void)
{
unsigned int est_freq, flags;
local_irq_save(flags);
unsigned int est_freq;
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
......@@ -114,6 +112,4 @@ void __init plat_time_init(void)
(est_freq % 1000000) * 100 / 1000000);
cpu_khz = est_freq / 1000;
local_irq_restore(flags);