Commit 51e02b02 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle

MIPS: Alchemy: Rewrite GPIO support.

The current in-kernel Alchemy GPIO support is far too inflexible for
all my use cases.  To address this, the following changes are made:

* create generic functions which deal with manipulating the on-chip
  GPIO1/2 blocks.  Such functions are universally useful.
* Macros for GPIO2 shared interrupt management and block control.
* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.

  If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
  compatibility by directly inlining the GPIO1/2 functions.  GPIO access
  is limited to on-chip ones and they can be accessed as documented in
  the datasheets (GPIO0-31 and 200-215).

  If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
  one for GPIO2, are registered.  GPIOs can still be accessed by using
  the numberspace established in the databooks.

  However this is not yet flexible enough for my uses:  My Alchemy
  systems have a documented "external" gpio interface (fixed, different
  numberspace) and can support a variety of baseboards, some of which
  are equipped with I2C gpio expanders.  I want to be able to provide
  the default 16 GPIOs of the CPU board numbered as 0..15 and also
  support gpio expanders, if present, starting as gpio16.

  To achieve this, a new Kconfig symbol for Alchemy is introduced,
  CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
  that they don't want the Alchemy numberspace exposed to the outside
  world, but instead want to provide their own.  Boards are now respon-
  sible for providing the linux gpio interface glue code (either in a
  custom gpio.h header (in board include directory) or with gpio_chips).

  To make the board-specific inlined gpio functions work, the MIPS
  Makefile must be changed so that the mach-au1x00/gpio.h header is
  included _after_ the board headers, by moving the inclusion of
  the mach-au1x00/ to the end of the header list.

  See arch/mips/include/asm/mach-au1x00/gpio.h for more info.
Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Acked-by: default avatarFlorian Fainelli <florian@openwrt.org>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent eeb09e65
......@@ -183,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
# Common Alchemy Au1x00 stuff
#
core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
#
# AMD Alchemy Pb1000 eval board
......@@ -281,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
# must be last for Alchemy systems for GPIO to work properly
cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
#
# Cobalt Server
#
......
# au1000-style gpio
config ALCHEMY_GPIO_AU1000
bool
# select this in your board config if you don't want to use the gpio
# namespace as documented in the manuals. In this case however you need
# to create the necessary gpio_* functions in your board code/headers!
# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
config ALCHEMY_GPIO_INDIRECT
def_bool n
choice
prompt "Machine type"
depends on MACH_ALCHEMY
......@@ -108,22 +119,27 @@ endchoice
config SOC_AU1000
bool
select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1100
bool
select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1500
bool
select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1550
bool
select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1200
bool
select SOC_AU1X00
select ALCHEMY_GPIO_AU1000
config SOC_AU1X00
bool
......@@ -134,4 +150,5 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select ARCH_REQUIRE_GPIOLIB
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
......@@ -7,7 +7,14 @@
obj-y += prom.o irq.o puts.o time.o reset.o \
clocks.o platform.o power.o setup.o \
sleeper.o dma.o dbdma.o gpio.o
sleeper.o dma.o dbdma.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
ifeq ($(CONFIG_GPIOLIB),y)
obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
endif
endif
obj-$(CONFIG_PCI) += pci.o
......
/*
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support
* GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -23,8 +23,8 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Notes :
* au1000 SoC have only one GPIO line : GPIO1
* others have a second one : GPIO2
* au1000 SoC have only one GPIO block : GPIO1
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
*/
#include <linux/kernel.h>
......@@ -34,168 +34,97 @@
#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h>
struct au1000_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;
};
#include <asm/mach-au1x00/gpio.h>
#if !defined(CONFIG_SOC_AU1000)
static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
static int gpio2_get(struct gpio_chip *chip, unsigned offset)
{
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
}
static void au1000_gpio2_set(struct gpio_chip *chip,
unsigned offset, int value)
static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
{
u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
}
static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
u32 mask = 1 << offset;
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp &= ~mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
local_irq_restore(flags);
return 0;
return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
}
static int au1000_gpio2_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
u32 mask = 1 << offset;
u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp |= mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
value);
}
return 0;
static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
{
return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
}
#endif /* !defined(CONFIG_SOC_AU1000) */
static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
static int gpio1_get(struct gpio_chip *chip, unsigned offset)
{
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
}
static void au1000_gpio1_set(struct gpio_chip *chip,
static void gpio1_set(struct gpio_chip *chip,
unsigned offset, int value)
{
u32 mask = 1 << offset;
u32 reg_offset;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
if (value)
reg_offset = AU1000_GPIO1_OUT;
else
reg_offset = AU1000_GPIO1_CLR;
local_irq_save(flags);
writel(mask, gpch->regbase + reg_offset);
local_irq_restore(flags);
alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
}
static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_ST);
return 0;
return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
}
static int au1000_gpio1_direction_output(struct gpio_chip *chip,
static int gpio1_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
au1000_gpio1_set(chip, offset, value);
return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
value);
}
return 0;
static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
{
return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
}
struct au1000_gpio_chip au1000_gpio_chip[] = {
struct gpio_chip alchemy_gpio_chip[] = {
[0] = {
.regbase = (void __iomem *)SYS_BASE,
.chip = {
.label = "au1000-gpio1",
.direction_input = au1000_gpio1_direction_input,
.direction_output = au1000_gpio1_direction_output,
.get = au1000_gpio1_get,
.set = au1000_gpio1_set,
.base = 0,
.ngpio = 32,
},
.label = "alchemy-gpio1",
.direction_input = gpio1_direction_input,
.direction_output = gpio1_direction_output,
.get = gpio1_get,
.set = gpio1_set,
.to_irq = gpio1_to_irq,
.base = ALCHEMY_GPIO1_BASE,
.ngpio = ALCHEMY_GPIO1_NUM,
},
#if !defined(CONFIG_SOC_AU1000)
[1] = {
.regbase = (void __iomem *)GPIO2_BASE,
.chip = {
.label = "au1000-gpio2",
.direction_input = au1000_gpio2_direction_input,
.direction_output = au1000_gpio2_direction_output,
.get = au1000_gpio2_get,
.set = au1000_gpio2_set,
.base = AU1XXX_GPIO_BASE,
.ngpio = 32,
},
.label = "alchemy-gpio2",
.direction_input = gpio2_direction_input,
.direction_output = gpio2_direction_output,
.get = gpio2_get,
.set = gpio2_set,
.to_irq = gpio2_to_irq,
.base = ALCHEMY_GPIO2_BASE,
.ngpio = ALCHEMY_GPIO2_NUM,
},
#endif
};
static int __init au1000_gpio_init(void)
static int __init alchemy_gpiolib_init(void)
{
gpiochip_add(&au1000_gpio_chip[0].chip);
gpiochip_add(&alchemy_gpio_chip[0]);
#if !defined(CONFIG_SOC_AU1000)
gpiochip_add(&au1000_gpio_chip[1].chip);
gpiochip_add(&alchemy_gpio_chip[1]);
#endif
return 0;
}
arch_initcall(au1000_gpio_init);
arch_initcall(alchemy_gpiolib_init);
/*
* GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
*
* Copyright (c) 2009 Manuel Lauss.
*
* Licensed under the terms outlined in the file COPYING.
*/
#ifndef _ALCHEMY_GPIO_AU1000_H_
#define _ALCHEMY_GPIO_AU1000_H_
#include <asm/mach-au1x00/au1000.h>
/* The default GPIO numberspace as documented in the Alchemy manuals.
* GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
*/
#define ALCHEMY_GPIO1_BASE 0
#define ALCHEMY_GPIO2_BASE 200
#define ALCHEMY_GPIO1_NUM 32
#define ALCHEMY_GPIO2_NUM 16
#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
static inline int au1000_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1000_gpio2_to_irq(int gpio)
{
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1000
static inline int au1000_irq_to_gpio(int irq)
{
if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
return -ENXIO;
}
#endif
static inline int au1500_gpio1_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO1_BASE;
switch (gpio) {
case 0 ... 15:
case 20:
case 23 ... 28: return MAKE_IRQ(1, gpio);
}
return -ENXIO;
}
static inline int au1500_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1500
static inline int au1500_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_15:
case AU1500_GPIO_20:
case AU1500_GPIO_23 ... AU1500_GPIO_28:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1500_GPIO_200 ... AU1500_GPIO_203:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
case AU1500_GPIO_204 ... AU1500_GPIO_205:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
case AU1500_GPIO_206 ... AU1500_GPIO_207:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
case AU1500_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + 8;
}
return -ENXIO;
}
#endif
static inline int au1100_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1100_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
if ((gpio >= 8) && (gpio <= 15))
return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
}
#ifdef CONFIG_SOC_AU1100
static inline int au1100_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_31:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1100_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + 8;
}
return -ENXIO;
}
#endif
static inline int au1550_gpio1_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO1_BASE;
switch (gpio) {
case 0 ... 15:
case 20 ... 28: return MAKE_IRQ(1, gpio);
case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
}
return -ENXIO;
}
static inline int au1550_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0: return MAKE_IRQ(1, 16);
case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1550
static inline int au1550_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_15:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1550_GPIO_200:
case AU1500_GPIO_201_205:
return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
case AU1500_GPIO_16 ... AU1500_GPIO_28:
return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
}
return -ENXIO;
}
#endif
static inline int au1200_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1200_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
case 3: return MAKE_IRQ(0, 22);
case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1200
static inline int au1200_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_31:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1200_GPIO_200 ... AU1200_GPIO_202:
return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
case AU1200_GPIO_203:
return ALCHEMY_GPIO2_BASE + 3;
case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
}
return -ENXIO;
}
#endif
/*
* GPIO1 block macros for common linux gpio functions.
*/
static inline void alchemy_gpio1_set_value(int gpio, int v)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
au_writel(mask, r);
au_sync();
}
static inline int alchemy_gpio1_get_value(int gpio)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
return au_readl(SYS_PINSTATERD) & mask;
}
static inline int alchemy_gpio1_direction_input(int gpio)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
au_writel(mask, SYS_TRIOUTCLR);
au_sync();
return 0;
}
static inline int alchemy_gpio1_direction_output(int gpio, int v)
{
/* hardware switches to "output" mode when one of the two
* "set_value" registers is accessed.
*/
alchemy_gpio1_set_value(gpio, v);
return 0;
}
static inline int alchemy_gpio1_is_valid(int gpio)
{
return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
}
static inline int alchemy_gpio1_to_irq(int gpio)
{
#if defined(CONFIG_SOC_AU1000)
return au1000_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1100)
return au1100_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1500)
return au1500_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1550)
return au1550_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1200)
return au1200_gpio1_to_irq(gpio);
#else
return -ENXIO;
#endif
}
/*
* GPIO2 block macros for common linux GPIO functions. The 'gpio'
* parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
*/
static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
unsigned long d = au_readl(GPIO2_DIR);
if (to_out)
d |= mask;
else
d &= ~mask;
au_writel(d, GPIO2_DIR);
au_sync();
}
static inline void alchemy_gpio2_set_value(int gpio, int v)
{
unsigned long mask;
mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
au_writel(mask, GPIO2_OUTPUT);
au_sync();
}
static inline int alchemy_gpio2_get_value(int gpio)
{
return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
}
static inline int alchemy_gpio2_direction_input(int gpio)
{