Commit 50743298 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: use the new masked bit macro some more



I've missed this one.

v2: Chris Wilson noticed another register.
v3: Color choice improvements.
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 624f8698
...@@ -3721,12 +3721,8 @@ i915_gem_load(struct drm_device *dev) ...@@ -3721,12 +3721,8 @@ i915_gem_load(struct drm_device *dev)
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */ /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
if (IS_GEN3(dev)) { if (IS_GEN3(dev)) {
u32 tmp = I915_READ(MI_ARB_STATE); I915_WRITE(MI_ARB_STATE,
if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
/* arb state is a masked write, so set bit + bit in mask */
tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
I915_WRITE(MI_ARB_STATE, tmp);
}
} }
dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
......
...@@ -570,7 +570,6 @@ ...@@ -570,7 +570,6 @@
#define LM_BURST_LENGTH 0x00000700 #define LM_BURST_LENGTH 0x00000700
#define LM_FIFO_WATERMARK 0x0000001F #define LM_FIFO_WATERMARK 0x0000001F
#define MI_ARB_STATE 0x020e4 /* 915+ only */ #define MI_ARB_STATE 0x020e4 /* 915+ only */
#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data /* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default * fetches. This is not turned on by default
...@@ -635,7 +634,6 @@ ...@@ -635,7 +634,6 @@
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */ #define CACHE_MODE_0 0x02120 /* 915+ only */
#define CM0_MASK_SHIFT 16
#define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_IZ_OPT_DISABLE (1<<6)
#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_ZR_OPT_DISABLE (1<<5)
#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
......
...@@ -2663,9 +2663,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) ...@@ -2663,9 +2663,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0);
/* clear masked bit */
I915_WRITE(CACHE_MODE_0, I915_WRITE(CACHE_MODE_0,
CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT); _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
I915_WRITE(GEN6_UCGCTL1, I915_WRITE(GEN6_UCGCTL1,
I915_READ(GEN6_UCGCTL1) | I915_READ(GEN6_UCGCTL1) |
......
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