Commit 4eb0c00b authored by David S. Miller's avatar David S. Miller
Browse files

sparc64: Add a comment about why we only use certain memory barriers these days.



Based upon feedback from Mathieu Desnoyers.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 03717e3d
...@@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ ...@@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
: : : "memory"); \ : : : "memory"); \
} while (0) } while (0)
/* The kernel always executes in TSO memory model these days,
* and furthermore most sparc64 chips implement more stringent
* memory ordering than required by the specifications.
*/
#define mb() membar_safe("#StoreLoad") #define mb() membar_safe("#StoreLoad")
#define rmb() __asm__ __volatile__("":::"memory") #define rmb() __asm__ __volatile__("":::"memory")
#define wmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory")
......
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