Commit 4c3ea371 authored by Jon Callan's avatar Jon Callan Committed by Catalin Marinas
Browse files

RealView: Add Cortex-A9 support to the EB board



This patch adds the necessary definitions and Kconfig entries to enable
Cortex-A9 (ARMv7 SMP) tiles on the RealView/EB board.
Signed-off-by: default avatarJon Callan <Jon.Callan@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>

parent 8aa2da87
......@@ -782,7 +782,7 @@ config HOTPLUG_CPU
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP)
default y
help
Enable support for local timers on SMP platforms, rather then the
......
......@@ -7,6 +7,13 @@ config MACH_REALVIEW_EB
help
Include support for the ARM(R) RealView Emulation Baseboard platform.
config REALVIEW_EB_A9MP
bool "Support Multicore Cortex-A9"
depends on MACH_REALVIEW_EB
select CPU_V7
help
Enable support for the Cortex-A9MPCore tile on the Realview platform.
config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore tile"
depends on MACH_REALVIEW_EB
......
......@@ -163,7 +163,7 @@
#define NR_IRQS NR_IRQS_EB
#endif
#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \
&& (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
#undef MAX_GIC_NR
#define MAX_GIC_NR NR_GIC_EB11MP
......@@ -177,6 +177,7 @@
#define REALVIEW_EB_PROC_ARM9 0x02000000
#define REALVIEW_EB_PROC_ARM11 0x04000000
#define REALVIEW_EB_PROC_ARM11MP 0x06000000
#define REALVIEW_EB_PROC_A9MP 0x0C000000
#define check_eb_proc(proc_type) \
((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
......@@ -188,4 +189,10 @@
#define core_tile_eb11mp() 0
#endif
#ifdef CONFIG_REALVIEW_EB_A9MP
#define core_tile_a9mp() check_eb_proc(REALVIEW_EB_PROC_A9MP)
#else
#define core_tile_a9mp() 0
#endif
#endif /* __ASM_ARCH_BOARD_EB_H */
......@@ -36,7 +36,8 @@ static unsigned int __init get_core_count(void)
unsigned int ncores;
void __iomem *scu_base = 0;
if (machine_is_realview_eb() && core_tile_eb11mp())
if (machine_is_realview_eb() &&
(core_tile_eb11mp() || core_tile_a9mp()))
scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
else if (machine_is_realview_pb11mp())
scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
......@@ -58,7 +59,8 @@ static void scu_enable(void)
u32 scu_ctrl;
void __iomem *scu_base;
if (machine_is_realview_eb() && core_tile_eb11mp())
if (machine_is_realview_eb() &&
(core_tile_eb11mp() || core_tile_a9mp()))
scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
else if (machine_is_realview_pb11mp())
scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
......@@ -88,7 +90,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
if (machine_is_realview_eb() && core_tile_eb11mp())
if (machine_is_realview_eb() &&
(core_tile_eb11mp() || core_tile_a9mp()))
gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
else if (machine_is_realview_pb11mp())
gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
......@@ -232,7 +235,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
* dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
* realview_timer_init
*/
if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
if ((machine_is_realview_eb() &&
(core_tile_eb11mp() || core_tile_a9mp())) ||
machine_is_realview_pb11mp())
local_timer_setup(cpu);
#endif
......
......@@ -108,7 +108,7 @@ static struct map_desc realview_eb11mp_io_desc[] __initdata = {
static void __init realview_eb_map_io(void)
{
iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
if (core_tile_eb11mp())
if (core_tile_eb11mp() || core_tile_a9mp())
iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
}
......@@ -274,7 +274,7 @@ static int eth_device_register(void)
static void __init gic_init_irq(void)
{
if (core_tile_eb11mp()) {
if (core_tile_eb11mp() || core_tile_a9mp()) {
unsigned int pldctrl;
/* new irq mode */
......@@ -342,7 +342,7 @@ static void __init realview_eb_timer_init(void)
timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
if (core_tile_eb11mp()) {
if (core_tile_eb11mp() || core_tile_a9mp()) {
#ifdef CONFIG_LOCAL_TIMERS
twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
twd_size = REALVIEW_EB11MP_TWD_SIZE;
......@@ -362,7 +362,7 @@ static void __init realview_eb_init(void)
{
int i;
if (core_tile_eb11mp()) {
if (core_tile_eb11mp() || core_tile_a9mp()) {
realview_eb11mp_fixup();
#ifdef CONFIG_CACHE_L2X0
......
......@@ -745,7 +745,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
config CACHE_L2X0
bool "Enable the L2x0 outer cache controller"
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
default y
select OUTER_CACHE
help
......
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