Commit 48d10bda authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'usb-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB updates from Greg KH:
 "Here is the big USB patchset for 4.6-rc1.

  The normal mess is here, gadget and xhci fixes and updates, and lots
  of other driver updates and cleanups as well.  Full details are in the
  shortlog.

  All have been in linux-next for a while with no reported issues"

* tag 'usb-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (266 commits)
  USB: core: let USB device know device node
  usb: devio: Add ioctl to disallow detaching kernel USB drivers.
  usb: gadget: f_acm: Fix configfs attr name
  usb: udc: lpc32xx: remove USB PLL and USB OTG clock management
  usb: udc: lpc32xx: remove direct access to clock controller registers
  usb: udc: lpc32xx: switch to clock prepare/unprepare model
  usb: renesas_usbhs: gadget: fix giveback status code in usbhsg_pipe_disable()
  usb: gadget: renesas_usb3: Use ARCH_RENESAS
  usb: dwc2: Fix issues in dwc2_complete_non_isoc_xfer_ddma()
  usb: dwc2: Add support for Lantiq ARX and XRX SoCs
  usb: phy: generic: Handle late registration of gadget
  usb: gadget: bdc_udc: fix race condition in bdc_udc_exit()
  usb: musb: core: added missing const qualifier to musb_hdrc_platform_data::config
  usb: dwc2: Move host-specific core functions into hcd.c
  usb: dwc2: Move register save and restore functions
  usb: dwc2: Use kmem_cache_free()
  usb: dwc2: host: If using uframe scheduler, end splits better
  usb: dwc2: host: Totally redo the microframe scheduler
  usb: dwc2: host: Properly set even/odd frame
  usb: dwc2: host: Add dwc2_hcd_get_future_frame_number() call
  ...
parents 96b9b1c9 ce53bfc4
......@@ -732,6 +732,18 @@ usbdev_ioctl (int fd, int ifno, unsigned request, void *param)
or SET_INTERFACE.
</para></warning></listitem></varlistentry>
<varlistentry><term>USBDEVFS_DROP_PRIVILEGES</term>
<listitem><para>This is used to relinquish the ability
to do certain operations which are considered to be
privileged on a usbfs file descriptor.
This includes claiming arbitrary interfaces, resetting
a device on which there are currently claimed interfaces
from other users, and issuing USBDEVFS_IOCTL calls.
The ioctl parameter is a 32 bit mask of interfaces
the user is allowed to claim on this file descriptor.
You may issue this ioctl more than one time to narrow
said mask.
</para></listitem></varlistentry>
</variablelist>
</sect2>
......
......@@ -7,33 +7,26 @@ Required properties:
- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC.
- reg: offset and length of the partial USB 2.0 Host register block.
- reg-names: must be "usb2_host".
- clocks: clock phandle and specifier pair(s).
- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
Optional properties:
To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
combined, the device tree node should set HSUSB properties to reg and reg-names
properties. This is because HSUSB has registers to select USB 2.0 host or
peripheral at that channel:
- reg: offset and length of the partial HSUSB register block.
- reg-names: must be "hsusb".
combined, the device tree node should set interrupt properties to use the
channel as USB OTG:
- interrupts: interrupt specifier for the PHY.
Example (R-Car H3):
usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a7795";
reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
reg-names = "usb2_host", "hsusb";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
<&mstp7_clks R8A7795_CLK_HSUSB>;
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
};
usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a7795";
reg = <0 0xee0a0200 0 0x700>;
reg-names = "usb2_host";
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
};
Rockchip specific extensions to the Analogix Display Port PHY
------------------------------------
Required properties:
- compatible : should be one of the following supported values:
- "rockchip.rk3288-dp-phy"
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
- rockchip,grf: phandle to the syscon managing the "general register files"
- #phy-cells : from the generic PHY bindings, must be 0;
Example:
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
Rockchip EMMC PHY
-----------------------
Required properties:
- compatible: rockchip,rk3399-emmc-phy
- rockchip,grf : phandle to the syscon managing the "general
register files"
- #phy-cells: must be 0
- reg: PHY configure reg address offset in "general
register files"
Example:
emmcphy: phy {
compatible = "rockchip,rk3399-emmc-phy";
rockchip,grf = <&grf>;
reg = <0xf780>;
#phy-cells = <0>;
};
......@@ -2,7 +2,14 @@
Required properties:
- compatible: should be one of:
"fsl,imx23-usb"
"fsl,imx27-usb"
"fsl,imx28-usb"
"fsl,imx6q-usb"
"fsl,imx6sl-usb"
"fsl,imx6sx-usb"
"fsl,imx6ul-usb"
"fsl,imx7d-usb"
"lsi,zevio-usb"
"qcom,ci-hdrc"
"chipidea,usb2"
......@@ -53,6 +60,22 @@ Optional properties:
be specified.
- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
low power mode and gating the PHY clock.
- non-zero-ttctrl-ttha: after setting this property, the value of register
ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
value. It needs to be very carefully for setting this property, it is
recommended that consult with your IC engineer before setting this value.
On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
property only affects siTD.
If this property is not set, the max packet size is 1023 bytes, and if
the total of packet size for pervious transactions are more than 256 bytes,
it can't accept any transactions within this frame. The use case is single
transaction, but higher frame rate.
If this property is set, the max packet size is 188 bytes, it can handle
more transactions than above case, it can accept transactions until it
considers the left room size within frame is less than 188 bytes, software
needs to make sure it does not send more than 90%
maximum_periodic_data_per_frame. The use case is multiple transactions, but
less frame rate.
i.mx specific properties
- fsl,usbmisc: phandler of non-core register device, with one
......
......@@ -8,6 +8,8 @@ Required properties:
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
......
Generic USB Device Properties
Usually, we only use device tree for hard wired USB device.
The reference binding doc is from:
http://www.firmware.org/1275/bindings/usb/usb-1_0.ps
Required properties:
- compatible: usbVID,PID. The textual representation of VID, PID shall
be in lower case hexadecimal with leading zeroes suppressed. The
other compatible strings from the above standard binding could also
be used, but a device adhering to this binding may leave out all except
for usbVID,PID.
- reg: the port number which this device is connecting to, the range
is 1-31.
Example:
&usb1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hub: genesys@1 {
compatible = "usb5e3,608";
reg = <1>;
};
}
USB xHCI controllers
Required properties:
- compatible: should be one of "generic-xhci",
"marvell,armada-375-xhci", "marvell,armada-380-xhci",
"renesas,xhci-r8a7790", "renesas,xhci-r8a7791", "renesas,xhci-r8a7793",
"renesas,xhci-r8a7795" (deprecated: "xhci-platform").
- compatible: should be one or more of
- "generic-xhci" for generic XHCI device
- "marvell,armada-375-xhci" for Armada 375 SoCs
- "marvell,armada-380-xhci" for Armada 38x SoCs
- "renesas,xhci-r8a7790" for r8a7790 SoC
- "renesas,xhci-r8a7791" for r8a7791 SoC
- "renesas,xhci-r8a7793" for r8a7793 SoC
- "renesas,xhci-r8a7795" for r8a7795 SoC
- "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 compatible device
- "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device
- "xhci-platform" (deprecated)
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first
followed by the generic version.
- reg: should contain address and length of the standard XHCI
register set for the device.
- interrupts: one XHCI interrupt should be described here.
......
......@@ -3533,6 +3533,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
on Mark read-only kernel memory as read-only (default).
off Leave read-only kernel memory writable for debugging.
rockchip.usb_uart
Enable the uart passthrough on the designated usb port
on Rockchip SoCs. When active, the signals of the
debug-uart get routed to the D+ and D- pins of the usb
port and the regular usb controller gets disabled.
root= [KNL] Root filesystem
See name_to_dev_t comment in init/do_mounts.c.
......
......@@ -26,16 +26,17 @@ cat /sys/kernel/debug/ci_hdrc.0/registers
On B-device:
echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
if HNP polling is not supported, also need:
On A-device:
echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
B-device should take host role and enumrate A-device.
4) A-device switch back to host.
On B-device:
echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
or, by introducing HNP polling, B-Host can know when A-peripheral wish
to be host role, so this role switch also can be trigged in A-peripheral
side by answering the polling from B-Host, this can be done on A-device:
echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
A-device should switch back to host and enumrate B-device.
5) Remove B-device(unplug micro B plug) and insert again in 10 seconds,
......
#include <sys/ioctl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include <linux/usbdevice_fs.h>
/* For building without an updated set of headers */
#ifndef USBDEVFS_DROP_PRIVILEGES
#define USBDEVFS_DROP_PRIVILEGES _IOW('U', 30, __u32)
#define USBDEVFS_CAP_DROP_PRIVILEGES 0x40
#endif
void drop_privileges(int fd, uint32_t mask)
{
int res;
res = ioctl(fd, USBDEVFS_DROP_PRIVILEGES, &mask);
if (res)
printf("ERROR: USBDEVFS_DROP_PRIVILEGES returned %d\n", res);
else
printf("OK: privileges dropped!\n");
}
void reset_device(int fd)
{
int res;
res = ioctl(fd, USBDEVFS_RESET);
if (!res)
printf("OK: USBDEVFS_RESET succeeded\n");
else
printf("ERROR: reset failed! (%d - %s)\n",
-res, strerror(-res));
}
void claim_some_intf(int fd)
{
int i, res;
for (i = 0; i < 4; i++) {
res = ioctl(fd, USBDEVFS_CLAIMINTERFACE, &i);
if (!res)
printf("OK: claimed if %d\n", i);
else
printf("ERROR claiming if %d (%d - %s)\n",
i, -res, strerror(-res));
}
}
int main(int argc, char *argv[])
{
uint32_t mask, caps;
int c, fd;
fd = open(argv[1], O_RDWR);
if (fd < 0) {
printf("Failed to open file\n");
goto err_fd;
}
/*
* check if dropping privileges is supported,
* bail on systems where the capability is not present
*/
ioctl(fd, USBDEVFS_GET_CAPABILITIES, &caps);
if (!(caps & USBDEVFS_CAP_DROP_PRIVILEGES)) {
printf("DROP_PRIVILEGES not supported\n");
goto err;
}
/*
* Drop privileges but keep the ability to claim all
* free interfaces (i.e., those not used by kernel drivers)
*/
drop_privileges(fd, -1U);
printf("Available options:\n"
"[0] Exit now\n"
"[1] Reset device. Should fail if device is in use\n"
"[2] Claim 4 interfaces. Should succeed where not in use\n"
"[3] Narrow interface permission mask\n"
"Which option shall I run?: ");
while (scanf("%d", &c) == 1) {
switch (c) {
case 0:
goto exit;
case 1:
reset_device(fd);
break;
case 2:
claim_some_intf(fd);
break;
case 3:
printf("Insert new mask: ");
scanf("%x", &mask);
drop_privileges(fd, mask);
break;
default:
printf("I don't recognize that\n");
}
printf("Which test shall I run next?: ");
}
exit:
close(fd);
return 0;
err:
close(fd);
err_fd:
return 1;
}
......@@ -11316,7 +11316,7 @@ F: include/linux/mtd/ubi.h
F: include/uapi/mtd/ubi-user.h
USB ACM DRIVER
M: Oliver Neukum <oliver@neukum.org>
M: Oliver Neukum <oneukum@suse.com>
L: linux-usb@vger.kernel.org
S: Maintained
F: Documentation/usb/acm.txt
......@@ -11440,6 +11440,7 @@ M: Valentina Manea <valentina.manea.m@gmail.com>
M: Shuah Khan <shuah.kh@samsung.com>
L: linux-usb@vger.kernel.org
S: Maintained
F: Documentation/usb/usbip_protocol.txt
F: drivers/usb/usbip/
F: tools/usb/usbip/
......
......@@ -395,204 +395,6 @@
#define CRP_AD_CBE_BESL 20
#define CRP_AD_CBE_WRITE 0x00010000
/*
* USB Device Controller
*
* These are used by the USB gadget driver, so they don't follow the
* IXP4XX_ naming convetions.
*
*/
# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
/* UDC Undocumented - Reserved1 */
#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
/* UDC Undocumented - Reserved2 */
#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
/* UDC Undocumented - Reserved3 */
#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
/* UDC Control Register */
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
/* UDC Endpoint 0 Control/Status Register */
#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
/* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
/* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
/* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
/* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
/* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
/* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
/* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
/* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
/* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
/* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
/* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
/* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
/* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
/* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
/* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
/* UDC Frame Number Register High */
#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
/* UDC Frame Number Register Low */
#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
/* UDC Byte Count Reg 2 */
#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
/* UDC Byte Count Reg 4 */
#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
/* UDC Byte Count Reg 7 */
#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
/* UDC Byte Count Reg 9 */
#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
/* UDC Byte Count Reg 12 */
#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
/* UDC Byte Count Reg 14 */
#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
/* UDC Endpoint 0 Data Register */
#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
/* UDC Endpoint 1 Data Register */
#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
/* UDC Endpoint 2 Data Register */
#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
/* UDC Endpoint 3 Data Register */
#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
/* UDC Endpoint 4 Data Register */
#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
/* UDC Endpoint 5 Data Register */
#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
/* UDC Endpoint 6 Data Register */
#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
/* UDC Endpoint 7 Data Register */
#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
/* UDC Endpoint 8 Data Register */
#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
/* UDC Endpoint 9 Data Register */
#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
/* UDC Endpoint 10 Data Register */
#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
/* UDC Endpoint 11 Data Register */
#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
/* UDC Endpoint 12 Data Register */
#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
/* UDC Endpoint 13 Data Register */
#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
/* UDC Endpoint 14 Data Register */
#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
/* UDC Endpoint 15 Data Register */
#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
/* UDC Interrupt Control Register 0 */
#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
/* UDC Interrupt Control Register 1 */
#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
/* UDC Status Interrupt Register 0 */
#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
/* UDC Status Interrupt Register 1 */
#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
/* "fuse" bits of IXP_EXP_CFG2 */
......
#ifndef _ASM_ARCH_PXA25X_UDC_H
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
#error "You can't include both PXA25x and PXA27x UDC support"
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */