Commit 47740eb8 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Enable CLO / CLZ instructions via separate CPU property



This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do
not implement the full MIPS32 / MIPS64 architecture.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5d57c31e
...@@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word) ...@@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word)
int num; int num;
if (BITS_PER_LONG == 32 && if (BITS_PER_LONG == 32 &&
__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__( __asm__(
" .set push \n" " .set push \n"
" .set mips32 \n" " .set mips32 \n"
...@@ -644,7 +644,7 @@ static inline int fls(int x) ...@@ -644,7 +644,7 @@ static inline int fls(int x)
{ {
int r; int r;
if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__("clz %0, %1" : "=r" (x) : "r" (x)); __asm__("clz %0, %1" : "=r" (x) : "r" (x));
return 32 - x; return 32 - x;
......
...@@ -147,6 +147,15 @@ ...@@ -147,6 +147,15 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2) cpu_has_mips64r1 | cpu_has_mips64r2)
/*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/
# ifndef cpu_has_clo_clz
# define cpu_has_clo_clz cpu_has_mips_r
# endif
#ifndef cpu_has_dsp #ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#endif #endif
......
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