From 444ad82bc3eaa554be40d22dc248e58aeefd54d9 Mon Sep 17 00:00:00 2001
From: Michael Hennerich <michael.hennerich@analog.com>
Date: Tue, 22 Jan 2008 18:38:02 +0800
Subject: [PATCH] [Blackfin] arch: Add proper SW System Reset delay sequence
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
---
arch/blackfin/kernel/reboot.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 06501a594dda..483f93dfc1b5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -19,6 +19,11 @@
#define SYSCR_VAL 0x10
#endif
+/*
+ * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
+ */
+#define SWRST_DELAY (5 * 15)
+
/* A system soft reset makes external memory unusable
* so force this function into L1.
*/
@@ -34,11 +39,15 @@ void bfin_reset(void)
while (1) {
/* initiate system soft reset with magic 0x7 */
bfin_write_SWRST(0x7);
- bfin_read_SWRST();
- asm("ssync;");
+
+ /* Wait for System reset to actually reset, needs to be 5 SCLKs, */
+ /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */
+
+ asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n"
+ : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
+
/* clear system soft reset */
bfin_write_SWRST(0);
- bfin_read_SWRST();
asm("ssync;");
/* issue core reset */
asm("raise 1");
--
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