Commit 3bb99fe2 authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
Browse files

e1000e: consolidate two dbug macros into one simpler one



This patch depends on a previous one that cleans up redundant #includes.
Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d8014dbc
......@@ -309,7 +309,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
* indicates that the bootagent or EFI code has
* improperly left this bit enabled
*/
hw_dbg(hw, "Please update your 82571 Bootagent\n");
e_dbg("Please update your 82571 Bootagent\n");
}
ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
}
......@@ -483,7 +483,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
}
if (i == sw_timeout) {
hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n");
e_dbg("Driver can't access device - SMBI bit is set.\n");
hw->dev_spec.e82571.smb_counter++;
}
/* Get the FW semaphore. */
......@@ -501,7 +501,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
if (i == fw_timeout) {
/* Release semaphores */
e1000_put_hw_semaphore_82571(hw);
hw_dbg(hw, "Driver can't access the NVM\n");
e_dbg("Driver can't access the NVM\n");
return -E1000_ERR_NVM;
}
......@@ -708,7 +708,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
hw_dbg(hw, "nvm parameter(s) out of bounds\n");
e_dbg("nvm parameter(s) out of bounds\n");
return -E1000_ERR_NVM;
}
......@@ -749,7 +749,7 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
timeout--;
}
if (!timeout) {
hw_dbg(hw, "MNG configuration cycle has not completed.\n");
e_dbg("MNG configuration cycle has not completed.\n");
return -E1000_ERR_RESET;
}
......@@ -848,9 +848,9 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
*/
ret_val = e1000e_disable_pcie_master(hw);
if (ret_val)
hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
e_dbg("PCI-E Master disable polling has failed.\n");
hw_dbg(hw, "Masking off all interrupts\n");
e_dbg("Masking off all interrupts\n");
ew32(IMC, 0xffffffff);
ew32(RCTL, 0);
......@@ -889,7 +889,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
ctrl = er32(CTRL);
hw_dbg(hw, "Issuing a global reset to MAC\n");
e_dbg("Issuing a global reset to MAC\n");
ew32(CTRL, ctrl | E1000_CTRL_RST);
if (hw->nvm.type == e1000_nvm_flash_hw) {
......@@ -955,12 +955,12 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
/* Initialize identification LED */
ret_val = e1000e_id_led_init(hw);
if (ret_val) {
hw_dbg(hw, "Error initializing identification LED\n");
e_dbg("Error initializing identification LED\n");
return ret_val;
}
/* Disabling VLAN filtering */
hw_dbg(hw, "Initializing the IEEE VLAN\n");
e_dbg("Initializing the IEEE VLAN\n");
e1000e_clear_vfta(hw);
/* Setup the receive address. */
......@@ -974,7 +974,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
e1000e_init_rx_addrs(hw, rar_count);
/* Zero out the Multicast HASH table */
hw_dbg(hw, "Zeroing the MTA\n");
e_dbg("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
......@@ -1383,7 +1383,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
*/
mac->serdes_link_state =
e1000_serdes_link_autoneg_progress;
hw_dbg(hw, "AN_UP -> AN_PROG\n");
e_dbg("AN_UP -> AN_PROG\n");
}
break;
......@@ -1401,7 +1401,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
(ctrl & ~E1000_CTRL_SLU));
mac->serdes_link_state =
e1000_serdes_link_autoneg_progress;
hw_dbg(hw, "FORCED_UP -> AN_PROG\n");
e_dbg("FORCED_UP -> AN_PROG\n");
}
break;
......@@ -1415,7 +1415,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
if (status & E1000_STATUS_LU) {
mac->serdes_link_state =
e1000_serdes_link_autoneg_complete;
hw_dbg(hw, "AN_PROG -> AN_UP\n");
e_dbg("AN_PROG -> AN_UP\n");
} else {
/*
* Disable autoneg, force link up and
......@@ -1430,12 +1430,12 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
ret_val =
e1000e_config_fc_after_link_up(hw);
if (ret_val) {
hw_dbg(hw, "Error config flow control\n");
e_dbg("Error config flow control\n");
break;
}
mac->serdes_link_state =
e1000_serdes_link_forced_up;
hw_dbg(hw, "AN_PROG -> FORCED_UP\n");
e_dbg("AN_PROG -> FORCED_UP\n");
}
mac->serdes_has_link = true;
break;
......@@ -1450,14 +1450,14 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
(ctrl & ~E1000_CTRL_SLU));
mac->serdes_link_state =
e1000_serdes_link_autoneg_progress;
hw_dbg(hw, "DOWN -> AN_PROG\n");
e_dbg("DOWN -> AN_PROG\n");
break;
}
} else {
if (!(rxcw & E1000_RXCW_SYNCH)) {
mac->serdes_has_link = false;
mac->serdes_link_state = e1000_serdes_link_down;
hw_dbg(hw, "ANYSTATE -> DOWN\n");
e_dbg("ANYSTATE -> DOWN\n");
} else {
/*
* We have sync, and can tolerate one
......@@ -1469,7 +1469,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
if (rxcw & E1000_RXCW_IV) {
mac->serdes_link_state = e1000_serdes_link_down;
mac->serdes_has_link = false;
hw_dbg(hw, "ANYSTATE -> DOWN\n");
e_dbg("ANYSTATE -> DOWN\n");
}
}
}
......@@ -1491,7 +1491,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
hw_dbg(hw, "NVM Read Error\n");
e_dbg("NVM Read Error\n");
return ret_val;
}
......
......@@ -48,9 +48,9 @@ struct e1000_info;
#ifdef DEBUG
#define e_dbg(format, arg...) \
e_printk(KERN_DEBUG , adapter, format, ## arg)
e_printk(KERN_DEBUG , hw->adapter, format, ## arg)
#else
#define e_dbg(format, arg...) do { (void)(adapter); } while (0)
#define e_dbg(format, arg...) do { (void)(hw); } while (0)
#endif
#define e_err(format, arg...) \
......
......@@ -394,8 +394,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
}
if (i == timeout) {
hw_dbg(hw,
"Driver can't access resource, SW_FW_SYNC timeout.\n");
e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
return -E1000_ERR_SWFW_SYNC;
}
......@@ -597,7 +596,7 @@ static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
timeout--;
}
if (!timeout) {
hw_dbg(hw, "MNG configuration cycle has not completed.\n");
e_dbg("MNG configuration cycle has not completed.\n");
return -E1000_ERR_RESET;
}
......@@ -630,7 +629,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
if (ret_val)
return ret_val;
hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
e_dbg("GG82563 PSCR: %X\n", phy_data);
ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
if (ret_val)
......@@ -648,7 +647,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
udelay(1);
if (hw->phy.autoneg_wait_to_complete) {
hw_dbg(hw, "Waiting for forced speed/duplex link "
e_dbg("Waiting for forced speed/duplex link "
"on GG82563 phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
......@@ -771,9 +770,9 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
*/
ret_val = e1000e_disable_pcie_master(hw);
if (ret_val)
hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
e_dbg("PCI-E Master disable polling has failed.\n");
hw_dbg(hw, "Masking off all interrupts\n");
e_dbg("Masking off all interrupts\n");
ew32(IMC, 0xffffffff);
ew32(RCTL, 0);
......@@ -785,7 +784,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
ctrl = er32(CTRL);
ret_val = e1000_acquire_phy_80003es2lan(hw);
hw_dbg(hw, "Issuing a global reset to MAC\n");
e_dbg("Issuing a global reset to MAC\n");
ew32(CTRL, ctrl | E1000_CTRL_RST);
e1000_release_phy_80003es2lan(hw);
......@@ -820,19 +819,19 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
/* Initialize identification LED */
ret_val = e1000e_id_led_init(hw);
if (ret_val) {
hw_dbg(hw, "Error initializing identification LED\n");
e_dbg("Error initializing identification LED\n");
return ret_val;
}
/* Disabling VLAN filtering */
hw_dbg(hw, "Initializing the IEEE VLAN\n");
e_dbg("Initializing the IEEE VLAN\n");
e1000e_clear_vfta(hw);
/* Setup the receive address. */
e1000e_init_rx_addrs(hw, mac->rar_entry_count);
/* Zero out the Multicast HASH table */
hw_dbg(hw, "Zeroing the MTA\n");
e_dbg("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
......@@ -989,7 +988,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
/* SW Reset the PHY so all changes take effect */
ret_val = e1000e_commit_phy(hw);
if (ret_val) {
hw_dbg(hw, "Error Resetting the PHY\n");
e_dbg("Error Resetting the PHY\n");
return ret_val;
}
......
......@@ -925,15 +925,4 @@ struct e1000_hw {
} dev_spec;
};
#ifdef DEBUG
#define hw_dbg(hw, format, arg...) \
printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
#else
static inline int __attribute__ ((format (printf, 2, 3)))
hw_dbg(struct e1000_hw *hw, const char *format, ...)
{
return 0;
}
#endif
#endif
......@@ -368,7 +368,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
/* Can't read flash registers if the register set isn't mapped. */
if (!hw->flash_address) {
hw_dbg(hw, "ERROR: Flash registers not mapped\n");
e_dbg("ERROR: Flash registers not mapped\n");
return -E1000_ERR_CONFIG;
}
......@@ -550,7 +550,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
*/
ret_val = e1000e_config_fc_after_link_up(hw);
if (ret_val)
hw_dbg(hw, "Error configuring flow control\n");
e_dbg("Error configuring flow control\n");
out:
return ret_val;
......@@ -644,7 +644,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
}
if (!timeout) {
hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
e_dbg("SW/FW/HW has locked the resource for too long.\n");
ret_val = -E1000_ERR_CONFIG;
goto out;
}
......@@ -664,7 +664,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
}
if (!timeout) {
hw_dbg(hw, "Failed to acquire the semaphore.\n");
e_dbg("Failed to acquire the semaphore.\n");
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
ew32(EXTCNF_CTRL, extcnf_ctrl);
ret_val = -E1000_ERR_CONFIG;
......@@ -773,12 +773,12 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
if (ret_val)
return ret_val;
hw_dbg(hw, "IFE PMC: %X\n", data);
e_dbg("IFE PMC: %X\n", data);
udelay(1);
if (phy->autoneg_wait_to_complete) {
hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
ret_val = e1000e_phy_has_link_generic(hw,
PHY_FORCE_LIMIT,
......@@ -788,7 +788,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
return ret_val;
if (!link)
hw_dbg(hw, "Link taking longer than expected.\n");
e_dbg("Link taking longer than expected.\n");
/* Try once more */
ret_val = e1000e_phy_has_link_generic(hw,
......@@ -1203,7 +1203,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
* leave the PHY in a bad state possibly resulting in no link.
*/
if (loop == 0)
hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
e_dbg("LAN_INIT_DONE not set, increase timeout\n");
/* Clear the Init Done bit for the next init event */
data = er32(STATUS);
......@@ -1274,7 +1274,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
return ret_val;
if (!link) {
hw_dbg(hw, "Phy info is only valid if link is up\n");
e_dbg("Phy info is only valid if link is up\n");
return -E1000_ERR_CONFIG;
}
......@@ -1604,7 +1604,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
return 0;
}
hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
e_dbg("Unable to determine valid NVM bank via EEC - "
"reading flash signature\n");
/* fall-thru */
default:
......@@ -1634,7 +1634,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
return 0;
}
hw_dbg(hw, "ERROR: No valid NVM bank present\n");
e_dbg("ERROR: No valid NVM bank present\n");
return -E1000_ERR_NVM;
}
......@@ -1662,7 +1662,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
(words == 0)) {
hw_dbg(hw, "nvm parameter(s) out of bounds\n");
e_dbg("nvm parameter(s) out of bounds\n");
ret_val = -E1000_ERR_NVM;
goto out;
}
......@@ -1671,7 +1671,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
e_dbg("Could not detect valid bank, assuming bank 0\n");
bank = 0;
}
......@@ -1697,7 +1697,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
out:
if (ret_val)
hw_dbg(hw, "NVM read error: %d\n", ret_val);
e_dbg("NVM read error: %d\n", ret_val);
return ret_val;
}
......@@ -1719,7 +1719,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
/* Check if the flash descriptor is valid */
if (hsfsts.hsf_status.fldesvalid == 0) {
hw_dbg(hw, "Flash descriptor invalid. "
e_dbg("Flash descriptor invalid. "
"SW Sequencing must be used.");
return -E1000_ERR_NVM;
}
......@@ -1769,7 +1769,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
hsfsts.hsf_status.flcdone = 1;
ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
} else {
hw_dbg(hw, "Flash controller busy, cannot get access");
e_dbg("Flash controller busy, cannot get access");
}
}
......@@ -1919,7 +1919,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
/* Repeat for some time before giving up. */
continue;
} else if (hsfsts.hsf_status.flcdone == 0) {
hw_dbg(hw, "Timeout error - flash cycle "
e_dbg("Timeout error - flash cycle "
"did not complete.");
break;
}
......@@ -1947,7 +1947,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
(words == 0)) {
hw_dbg(hw, "nvm parameter(s) out of bounds\n");
e_dbg("nvm parameter(s) out of bounds\n");
return -E1000_ERR_NVM;
}
......@@ -1998,7 +1998,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
*/
ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
e_dbg("Could not detect valid bank, assuming bank 0\n");
bank = 0;
}
......@@ -2072,7 +2072,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
*/
if (ret_val) {
/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
hw_dbg(hw, "Flash commit failed.\n");
e_dbg("Flash commit failed.\n");
nvm->ops.release_nvm(hw);
goto out;
}
......@@ -2128,7 +2128,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
out:
if (ret_val)
hw_dbg(hw, "NVM update error: %d\n", ret_val);
e_dbg("NVM update error: %d\n", ret_val);
return ret_val;
}
......@@ -2278,7 +2278,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
/* Repeat for some time before giving up. */
continue;
if (hsfsts.hsf_status.flcdone == 0) {
hw_dbg(hw, "Timeout error - flash cycle "
e_dbg("Timeout error - flash cycle "
"did not complete.");
break;
}
......@@ -2323,7 +2323,7 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
return ret_val;
for (program_retries = 0; program_retries < 100; program_retries++) {
hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
udelay(100);
ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
if (!ret_val)
......@@ -2458,7 +2458,7 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
hw_dbg(hw, "NVM Read Error\n");
e_dbg("NVM Read Error\n");
return ret_val;
}
......@@ -2588,10 +2588,10 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
*/
ret_val = e1000e_disable_pcie_master(hw);
if (ret_val) {
hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
e_dbg("PCI-E Master disable polling has failed.\n");
}
hw_dbg(hw, "Masking off all interrupts\n");
e_dbg("Masking off all interrupts\n");
ew32(IMC, 0xffffffff);
/*
......@@ -2643,7 +2643,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
}
ret_val = e1000_acquire_swflag_ich8lan(hw);
/* Whether or not the swflag was acquired, we need to reset the part */
hw_dbg(hw, "Issuing a global reset to ich8lan\n");
e_dbg("Issuing a global reset to ich8lan\n");
ew32(CTRL, (ctrl | E1000_CTRL_RST));
msleep(20);
......@@ -2663,7 +2663,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
hw_dbg(hw, "Auto Read Done did not complete\n");
e_dbg("Auto Read Done did not complete\n");
}
}
/* Dummy read to clear the phy wakeup bit after lcd reset */
......@@ -2725,7 +2725,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
/* Initialize identification LED */
ret_val = mac->ops.id_led_init(hw);
if (ret_val) {
hw_dbg(hw, "Error initializing identification LED\n");
e_dbg("Error initializing identification LED\n");
return ret_val;
}
......@@ -2733,7 +2733,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
e1000e_init_rx_addrs(hw, mac->rar_entry_count);
/* Zero out the Multicast HASH table */
hw_dbg(hw, "Zeroing the MTA\n");
e_dbg("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
......@@ -2879,7 +2879,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
*/
hw->fc.current_mode = hw->fc.requested_mode;
hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
e_dbg("After fix-ups FlowControl is now = %x\n",
hw->fc.current_mode);
/* Continue to configure the copper link. */
......@@ -3094,7 +3094,7 @@ void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
if (hw->mac.type != e1000_ich8lan) {
hw_dbg(hw, "Workaround applies to ICH8 only.\n");
e_dbg("Workaround applies to ICH8 only.\n");
return;
}
......@@ -3372,8 +3372,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
if (status & E1000_STATUS_PHYRA)
ew32(STATUS, status & ~E1000_STATUS_PHYRA);
else
hw_dbg(hw,
"PHY Reset Asserted not set - needs delay\n");
e_dbg("PHY Reset Asserted not set - needs delay\n");
}
e1000e_get_cfg_done(hw);
......@@ -3388,7 +3387,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
} else {
if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
/* Maybe we should do a basic PHY config */
hw_dbg(hw, "EEPROM not present\n");
e_dbg("EEPROM not present\n");
return -E1000_ERR_CONFIG;
}
}
......
......@@ -110,12 +110,12 @@ void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
u32 i;
/* Setup the receive address */
hw_dbg(hw, "Programming MAC Address into RAR[0]\n");
e_dbg("Programming MAC Address into RAR[0]\n");
e1000e_rar_set(hw, hw->mac.addr, 0);
/* Zero out the other (rar_entry_count - 1) receive addresses */
hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);
e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
for (i = 1; i < rar_count; i++) {
E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
e1e_flush();
......@@ -271,7 +271,7 @@ void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
for (; mc_addr_count > 0; mc_addr_count--) {
u32 hash_value, hash_reg, hash_bit, mta;
hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
hw_dbg(hw, "Hash value = 0x%03X\n", hash_value);
e_dbg("Hash value = 0x%03X\n", hash_value);
hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
hash_bit = hash_value & 0x1F;
mta = (1 << hash_bit);
......@@ -403,7 +403,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
*/
ret_val = e1000e_config_fc_after_link_up(hw);
if (ret_val) {
hw_dbg(hw, "Error configuring flow control\n");
e_dbg("Error configuring flow control\n");
}
return ret_val;
......@@ -443,7 +443,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
mac->autoneg_failed = 1;
return 0;
}
hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
/* Disable auto-negotiation in the TXCW register */
ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
......@@ -456,7 +456,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
/* Configure Flow Control after forcing link up. */
ret_val = e1000e_config_fc_after_link_up(hw);
if (ret_val) {
hw_dbg(hw, "Error configuring flow control\n");
e_dbg("Error configuring flow control\n");
return ret_val;
}
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
......@@ -466,7 +466,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
*/
hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
ew32(TXCW, mac->txcw);
ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
......@@ -508,7 +508,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
mac->autoneg_failed = 1;
return 0;
}
hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
/* Disable auto-negotiation in the TXCW register */