Commit 37b034a6 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvd0/disp: tidy up what we have so far


Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent ee41779e
......@@ -23,12 +23,12 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
nva3_copy.o nvc0_copy.o \
nv31_mpeg.o nv50_mpeg.o \
nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
nv50_cursor.o nv50_display.o \
nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
nv04_crtc.o nv04_display.o nv04_cursor.o \
nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
nv50_cursor.o nv50_display.o \
nvd0_display.o \
nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
nv10_gpio.o nv50_gpio.o \
nv50_calc.o \
nv04_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o \
......
......@@ -31,13 +31,10 @@
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"
#include "nouveau_dma.h"
#include "nouveau_fb.h"
#include "nv50_display.h"
#define MEM_SYNC 0xe0000001
#define MEM_VRAM 0xe0010000
#include "nouveau_dma.h"
struct nvd0_display {
struct nouveau_gpuobj *mem;
struct {
......@@ -56,7 +53,7 @@ nvd0_display(struct drm_device *dev)
return dev_priv->engine.display.priv;
}
static int
static inline int
evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
{
int ret = 0;
......@@ -237,7 +234,7 @@ nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
evo_data(push, 0x85000000);
evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
evo_data(push, MEM_VRAM);
evo_data(push, NvEvoVRAM);
} else {
evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
evo_data(push, 0x05000000);
......@@ -295,7 +292,7 @@ nvd0_crtc_commit(struct drm_crtc *crtc)
evo_data(push, 0x00000000);
evo_data(push, 0x00000000);
evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
evo_data(push, MEM_VRAM);
evo_data(push, NvEvoVRAM);
evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
evo_data(push, 0xffffff00);
evo_kick(push, crtc->dev, 0);
......@@ -958,23 +955,6 @@ nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
/******************************************************************************
* IRQ
*****************************************************************************/
static void
debug_irq(struct drm_device *dev, int i)
{
if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
NV_INFO(dev, "PDISP: modeset req %d\n", i);
NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
nv_rd32(dev, 0x6101d0),
nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
for (i = 0; i < 8; i++) {
NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
i < 4 ? "DAC" : "SOR", i,
nv_rd32(dev, 0x640180 + (i * 0x20)),
nv_rd32(dev, 0x660180 + (i * 0x20)));
}
}
}
static struct dcb_entry *
lookup_dcb(struct drm_device *dev, int id, u32 mc)
{
......@@ -1009,20 +989,11 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
}
static void
nvd0_display_unk1_handler(struct drm_device *dev)
nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
{
struct dcb_entry *dcb;
u32 mask, crtc;
int i;
mask = nv_rd32(dev, 0x6101d4);
crtc = 0;
if (!mask) {
mask = nv_rd32(dev, 0x6109d4);
crtc = 1;
}
debug_irq(dev, 1);
for (i = 0; mask && i < 8; i++) {
u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
if (!(mcc & (1 << crtc)))
......@@ -1041,21 +1012,12 @@ nvd0_display_unk1_handler(struct drm_device *dev)
}
static void
nvd0_display_unk2_handler(struct drm_device *dev)
nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
{
struct dcb_entry *dcb;
u32 mask, crtc, pclk;
u32 or, tmp;
u32 or, tmp, pclk;
int i;
mask = nv_rd32(dev, 0x6101d4);
crtc = 0;
if (!mask) {
mask = nv_rd32(dev, 0x6109d4);
crtc = 1;
}
debug_irq(dev, 2);
for (i = 0; mask && i < 8; i++) {
u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
if (!(mcc & (1 << crtc)))
......@@ -1113,20 +1075,11 @@ nvd0_display_unk2_handler(struct drm_device *dev)
}
static void
nvd0_display_unk4_handler(struct drm_device *dev)
nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
{
struct dcb_entry *dcb;
u32 mask, crtc;
int pclk, i;
mask = nv_rd32(dev, 0x6101d4);
crtc = 0;
if (!mask) {
mask = nv_rd32(dev, 0x6109d4);
crtc = 1;
}
debug_irq(dev, 4);
pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
for (i = 0; mask && i < 8; i++) {
......@@ -1152,13 +1105,35 @@ nvd0_display_bh(unsigned long data)
{
struct drm_device *dev = (struct drm_device *)data;
struct nvd0_display *disp = nvd0_display(dev);
u32 mask, crtc;
int i;
if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
nv_rd32(dev, 0x6101d0),
nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
for (i = 0; i < 8; i++) {
NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
i < 4 ? "DAC" : "SOR", i,
nv_rd32(dev, 0x640180 + (i * 0x20)),
nv_rd32(dev, 0x660180 + (i * 0x20)));
}
}
mask = nv_rd32(dev, 0x6101d4);
crtc = 0;
if (!mask) {
mask = nv_rd32(dev, 0x6109d4);
crtc = 1;
}
if (disp->modeset & 0x00000001)
nvd0_display_unk1_handler(dev);
nvd0_display_unk1_handler(dev, crtc, mask);
if (disp->modeset & 0x00000002)
nvd0_display_unk2_handler(dev);
nvd0_display_unk2_handler(dev, crtc, mask);
if (disp->modeset & 0x00000004)
nvd0_display_unk4_handler(dev);
nvd0_display_unk4_handler(dev, crtc, mask);
}
static void
......@@ -1324,7 +1299,7 @@ nvd0_display_init(struct drm_device *dev)
if (!push)
return -EBUSY;
evo_mthd(push, 0x0088, 1);
evo_data(push, MEM_SYNC);
evo_data(push, NvEvoSync);
evo_mthd(push, 0x0084, 1);
evo_data(push, 0x00000000);
evo_mthd(push, 0x0084, 1);
......@@ -1430,7 +1405,7 @@ nvd0_display_create(struct drm_device *dev)
nv_wo32(disp->mem, 0x100c, 0x00000000);
nv_wo32(disp->mem, 0x1010, 0x00000000);
nv_wo32(disp->mem, 0x1014, 0x00000000);
nv_wo32(disp->mem, 0x0000, MEM_SYNC);
nv_wo32(disp->mem, 0x0000, NvEvoSync);
nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
nv_wo32(disp->mem, 0x1020, 0x00000049);
......@@ -1439,7 +1414,7 @@ nvd0_display_create(struct drm_device *dev)
nv_wo32(disp->mem, 0x102c, 0x00000000);
nv_wo32(disp->mem, 0x1030, 0x00000000);
nv_wo32(disp->mem, 0x1034, 0x00000000);
nv_wo32(disp->mem, 0x0008, MEM_VRAM);
nv_wo32(disp->mem, 0x0008, NvEvoVRAM);
nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
nv_wo32(disp->mem, 0x1040, 0x00000009);
......
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