Commit 3795e0f6 authored by Sylwester Nawrocki's avatar Sylwester Nawrocki

clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition

Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER
mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register.
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent f0abd931
...@@ -5038,9 +5038,9 @@ static struct samsung_mux_clock cam1_mux_clks[] __initdata = { ...@@ -5038,9 +5038,9 @@ static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1), mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1), mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
/* MUX_SEL_CAM11 */ /* MUX_SEL_CAM11 */
MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
......
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