Commit 3109e550 authored by Kukjin Kim's avatar Kukjin Kim
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ARM: S5P64X0: Update Clock for S5P6440 and S5P6450



This patch updates regarding clock files for supporting S5P6440 and
S5P6450 with one kernel image. The mach-s5p64x0/clock.c is for common
of them and there are specific clock files for each SoCs.
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a2e0d624
/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6440 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
#define S5P_APLL_CON S5P_CLKREG(0x0C)
#define S5P_MPLL_CON S5P_CLKREG(0x10)
#define S5P_EPLL_CON S5P_CLKREG(0x14)
#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
#define S5P_CLK_OUT S5P_CLKREG(0x2C)
#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
#define S5P_AHB_CON0 S5P_CLKREG(0x100)
#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P_SWRESET S5P_CLKREG(0x114)
#define S5P_SYS_ID S5P_CLKREG(0x118)
#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
#define S5P_PWR_CFG S5P_CLKREG(0x804)
#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
#define S5P_STOP_CFG S5P_CLKREG(0x814)
#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
#define S5P_OSC_FREQ S5P_CLKREG(0x820)
#define S5P_OSC_STABLE S5P_CLKREG(0x824)
#define S5P_PWR_STABLE S5P_CLKREG(0x828)
#define S5P_MTC_STABLE S5P_CLKREG(0x830)
#define S5P_OTHERS S5P_CLKREG(0x900)
#define S5P_RST_STAT S5P_CLKREG(0x904)
#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
#define S5P_SLPEN S5P_CLKREG(0x930)
#define S5P_INFORM0 S5P_CLKREG(0xA00)
#define S5P_INFORM1 S5P_CLKREG(0xA04)
#define S5P_INFORM2 S5P_CLKREG(0xA08)
#define S5P_INFORM3 S5P_CLKREG(0xA0C)
/* CLKDIV0 */
#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
#define S5P_CLKDIV0_PCLK_SHIFT (12)
#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
#define S5P_CLKDIV0_HCLK_SHIFT (8)
#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
#define S5P_CLKDIV0_ARM_SHIFT (0)
/* CLKDIV3 */
#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
/* HCLK0 GATE Registers */
#define S5P_CLKCON_HCLK0_USB (1<<20)
#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
#define S5P_CLKCON_HCLK0_POST0 (1<<5)
/* HCLK1 GATE Registers */
#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
/* PCLK GATE Registers */
#define S5P_CLKCON_PCLK_IIS2 (1<<26)
#define S5P_CLKCON_PCLK_SPI1 (1<<22)
#define S5P_CLKCON_PCLK_SPI0 (1<<21)
#define S5P_CLKCON_PCLK_GPIO (1<<18)
#define S5P_CLKCON_PCLK_IIC0 (1<<17)
#define S5P_CLKCON_PCLK_TSADC (1<<12)
#define S5P_CLKCON_PCLK_PWM (1<<7)
#define S5P_CLKCON_PCLK_RTC (1<<6)
#define S5P_CLKCON_PCLK_WDT (1<<5)
#define S5P_CLKCON_PCLK_UART3 (1<<4)
#define S5P_CLKCON_PCLK_UART2 (1<<3)
#define S5P_CLKCON_PCLK_UART1 (1<<2)
#define S5P_CLKCON_PCLK_UART0 (1<<1)
/* SCLK0 GATE Registers */
#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
#define S5P_CLKCON_SCLK0_UART (1<<5)
/* SCLK1 GATE Registers */
/* MEM0 GATE Registers */
#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
/*OTHERS Resgister */
#define S5P_OTHERS_USB_SIG_MASK (1<<16)
#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
/* Compatibility defines */
#define ARM_CLK_DIV S5P_CLK_DIV0
#define ARM_DIV_RATIO_SHIFT 0
#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P6450 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6450.h>
static struct clksrc_clk clk_mout_dpll = {
.clk = {
.name = "mout_dpll",
.id = -1,
},
.sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
};
static u32 epll_div[][5] = {
{ 133000000, 27307, 55, 2, 2 },
{ 100000000, 43691, 41, 2, 2 },
{ 480000000, 0, 80, 2, 0 },
};
static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int epll_con, epll_con_k;
unsigned int i;
if (clk->rate == rate) /* Return if nothing changed */
return 0;
epll_con = __raw_readl(S5P64X0_EPLL_CON);
epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
epll_con_k &= ~(PLL90XX_KDIV_MASK);
epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
(epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
break;
}
}
if (i == ARRAY_SIZE(epll_div)) {
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
return -EINVAL;
}
__raw_writel(epll_con, S5P64X0_EPLL_CON);
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6450_epll_ops = {
.get_rate = s5p64x0_epll_get_rate,
.set_rate = s5p6450_epll_set_rate,
};
static struct clksrc_clk clk_dout_epll = {
.clk = {
.name = "dout_epll",
.id = -1,
.parent = &clk_mout_epll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
};
static struct clksrc_clk clk_mout_hclk_sel = {
.clk = {
.name = "mout_hclk_sel",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
};
static struct clk *clkset_hclk_list[] = {
&clk_mout_hclk_sel.clk,
&clk_armclk.clk,
};
static struct clksrc_sources clkset_hclk = {
.sources = clkset_hclk_list,
.nr_sources = ARRAY_SIZE(clkset_hclk_list),
};
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
},
.sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = {
.name = "clk_dout_pwm_ratio0",
.id = -1,
.parent = &clk_mout_hclk_sel.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
};
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = {
.name = "clk_pclk_to_wdt_pwm",
.id = -1,
.parent = &clk_dout_pwm_ratio0.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
.id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
};
/*
* The following clocks will be disabled during clock initialization. It is
* recommended to keep the following clocks disabled until the driver requests
* for enabling the clock.
*/
static struct clk init_clocks_disable[] = {
{
.name = "usbhost",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "usbotg",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "i2c",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}
};
/*
* The following clocks will be enabled during clock initialization.
*/
static struct clk init_clocks[] = {
{
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "uart",
.id = 0,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 2,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 3,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "timers",
.id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
},
};
static struct clk *clkset_uart_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_mali_list[] = {
&clk_mout_epll.clk,
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_mali = {
.sources = clkset_mali_list,
.nr_sources = ARRAY_SIZE(clkset_mali_list),
};
static struct clk *clkset_group2_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
};
static struct clksrc_sources clkset_group2 = {
.sources = clkset_group2_list,
.nr_sources = ARRAY_SIZE(clkset_group2_list),
};
static struct clk *clkset_dispcon_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
&clk_mout_dpll.clk,
};
static struct clksrc_sources clkset_dispcon = {
.sources = clkset_dispcon_list,
.nr_sources = ARRAY_SIZE(clkset_dispcon_list),
};
static struct clk *clkset_hsmmc44_list[] = {
&clk_dout_epll.clk,
&clk_dout_mpll.clk,
&clk_ext_xtal_mux,
&s5p_clk_27m,
&clk_48m,
};
static struct clksrc_sources clkset_hsmmc44 = {
.sources = clkset_hsmmc44_list,
.nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
};
static struct clk *clkset_sclk_audio0_list[] = {
[0] = &clk_dout_epll.clk,
[1] = &clk_dout_mpll.clk,
[2] = &clk_ext_xtal_mux,
[3] = NULL,
[4] = NULL,
};
static struct clksrc_sources clkset_sclk_audio0 = {
.sources = clkset_sclk_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
};
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
.id = -1,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
},
.sources = &clkset_sclk_audio0,
.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
.id = 0,
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",