Commit 3070fb88 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
  sh: clkfwk: Build fix for non-legacy CPG changes.
  sh: Use GCC __builtin_prefetch() to implement prefetch().
  sh: fix vsyscall compilation due to .eh_frame issue
  sh: avoid to flush all cache in sys_cacheflush
  sh: clkfwk: Disable init clk op for non-legacy clocks.
  sh: clkfwk: Kill off now unused algo_id in set_rate op.
  sh: clkfwk: Kill off unused clk_set_rate_ex().
parents 68ca92aa dfcd6e43
......@@ -79,10 +79,6 @@
</sect2>
</sect1>
</chapter>
<chapter id="clk">
<title>Clock Framework Extensions</title>
!Iinclude/linux/sh_clk.h
</chapter>
<chapter id="mach">
<title>Machine Specific Interfaces</title>
<sect1 id="dreamcast">
......
Clock framework on SuperH architecture
The framework on SH extends existing API by the function clk_set_rate_ex,
which prototype is as follows:
clk_set_rate_ex (struct clk *clk, unsigned long rate, int algo_id)
The algo_id parameter is used to specify algorithm used to recalculate clocks,
adjanced to clock, specified as first argument. It is assumed that algo_id==0
means no changes to adjanced clock
Internally, the clk_set_rate_ex forwards request to clk->ops->set_rate method,
if it is present in ops structure. The method should set the clock rate and adjust
all needed clocks according to the passed algo_id.
Exact values for algo_id are machine-dependent. For the sh7722, the following
values are defined:
NO_CHANGE = 0,
IUS_N1_N1, /* I:U = N:1, U:Sh = N:1 */
IUS_322, /* I:U:Sh = 3:2:2 */
IUS_522, /* I:U:Sh = 5:2:2 */
IUS_N11, /* I:U:Sh = N:1:1 */
SB_N1, /* Sh:B = N:1 */
SB3_N1, /* Sh:B3 = N:1 */
SB3_32, /* Sh:B3 = 3:2 */
SB3_43, /* Sh:B3 = 4:3 */
SB3_54, /* Sh:B3 = 5:4 */
BP_N1, /* B:P = N:1 */
IP_N1 /* I:P = N:1 */
Each of these constants means relation between clocks that can be set via the FRQCR
register
......@@ -220,8 +220,7 @@ static void pllc2_disable(struct clk *clk)
__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
}
static int pllc2_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
static int pllc2_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long value;
int idx;
......@@ -463,8 +462,7 @@ static int fsidiv_enable(struct clk *clk)
return 0;
}
static int fsidiv_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
{
int idx;
......
......@@ -199,10 +199,13 @@ extern unsigned long get_wchan(struct task_struct *p);
#define ARCH_HAS_PREFETCHW
static inline void prefetch(void *x)
{
__asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
__builtin_prefetch(x, 0, 3);
}
#define prefetchw(x) prefetch(x)
static inline void prefetchw(void *x)
{
__builtin_prefetch(x, 1, 3);
}
#endif
#endif /* __KERNEL__ */
......
......@@ -110,7 +110,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
return 0;
}
static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long frqcr3;
unsigned int tmp;
......
......@@ -88,7 +88,7 @@ asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op)
}
if (op & CACHEFLUSH_I)
flush_cache_all();
flush_icache_range(addr, addr+len);
up_read(&current->mm->mmap_sem);
return 0;
......
......@@ -8,9 +8,9 @@ __kernel_vsyscall:
* fill out .eh_frame -- PFM. */
.LEND_vsyscall:
.size __kernel_vsyscall,.-.LSTART_vsyscall
.previous
.section .eh_frame,"a",@progbits
.previous
.LCIE:
.ualong .LCIE_end - .LCIE_start
.LCIE_start:
......
......@@ -418,8 +418,11 @@ int clk_register(struct clk *clk)
list_add(&clk->sibling, &root_clks);
list_add(&clk->node, &clock_list);
#ifdef CONFIG_SH_CLK_CPG_LEGACY
if (clk->ops && clk->ops->init)
clk->ops->init(clk);
#endif
out_unlock:
mutex_unlock(&clock_list_sem);
......@@ -454,12 +457,6 @@ unsigned long clk_get_rate(struct clk *clk)
EXPORT_SYMBOL_GPL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return clk_set_rate_ex(clk, rate, 0);
}
EXPORT_SYMBOL_GPL(clk_set_rate);
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
{
int ret = -EOPNOTSUPP;
unsigned long flags;
......@@ -467,7 +464,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
spin_lock_irqsave(&clock_lock, flags);
if (likely(clk->ops && clk->ops->set_rate)) {
ret = clk->ops->set_rate(clk, rate, algo_id);
ret = clk->ops->set_rate(clk, rate);
if (ret != 0)
goto out_unlock;
} else {
......@@ -485,7 +482,7 @@ out_unlock:
return ret;
}
EXPORT_SYMBOL_GPL(clk_set_rate_ex);
EXPORT_SYMBOL_GPL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
......@@ -653,8 +650,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
clkp->ops->set_parent(clkp,
clkp->parent);
if (likely(clkp->ops->set_rate))
clkp->ops->set_rate(clkp,
rate, NO_CHANGE);
clkp->ops->set_rate(clkp, rate);
else if (likely(clkp->ops->recalc))
clkp->rate = clkp->ops->recalc(clkp);
}
......
......@@ -110,8 +110,7 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static int sh_clk_div6_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long value;
int idx;
......@@ -132,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk)
unsigned long value;
int ret;
ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
ret = sh_clk_div6_set_rate(clk, clk->rate);
if (ret == 0) {
value = __raw_readl(clk->enable_reg);
value &= ~0x100; /* clear stop bit to enable clock */
......@@ -253,7 +252,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
{
struct clk_div4_table *d4t = clk->priv;
unsigned long value;
......
......@@ -19,11 +19,13 @@ struct clk_mapping {
};
struct clk_ops {
#ifdef CONFIG_SH_CLK_CPG_LEGACY
void (*init)(struct clk *clk);
#endif
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
unsigned long (*recalc)(struct clk *clk);
int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
int (*set_rate)(struct clk *clk, unsigned long rate);
int (*set_parent)(struct clk *clk, struct clk *parent);
long (*round_rate)(struct clk *clk, unsigned long rate);
};
......@@ -67,36 +69,6 @@ int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);
/**
* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
* @clk: clock source
* @rate: desired clock rate in Hz
* @algo_id: algorithm id to be passed down to ops->set_rate
*
* Returns success (0) or negative errno.
*/
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
enum clk_sh_algo_id {
NO_CHANGE = 0,
IUS_N1_N1,
IUS_322,
IUS_522,
IUS_N11,
SB_N1,
SB3_N1,
SB3_32,
SB3_43,
SB3_54,
BP_N1,
IP_N1,
};
struct clk_div_mult_table {
unsigned int *divisors;
unsigned int nr_divisors;
......
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