Commit 2e89db75 authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
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serial: MPSC: Fix coding style and whitespace issues



Fix up mpsc.c to be aligned with Documentation/CodingStyle.  Also fix up some
whitespace issues.
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 79f85173
......@@ -93,9 +93,8 @@
#define MPSC_TXBE_SIZE dma_get_cache_alignment()
#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
dma_get_cache_alignment() /* for alignment */)
#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
+ MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
struct mpsc_rx_desc {
......@@ -266,8 +265,8 @@ struct mpsc_port_info *mpsc_device_remove(int index);
#define SDMA_DESC_CMDSTAT_EI (1<<23)
#define SDMA_DESC_CMDSTAT_O (1<<31)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
SDMA_DESC_CMDSTAT_EI)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
| SDMA_DESC_CMDSTAT_EI)
#define SDMA_SDC_RFT (1<<0)
#define SDMA_SDC_SFM (1<<1)
......@@ -291,10 +290,10 @@ struct mpsc_port_info *mpsc_device_remove(int index);
#define SDMA_1_CAUSE_TXBUF (1<<10)
#define SDMA_1_CAUSE_TXEND (1<<11)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
| SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
| SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
/* SDMA Interrupt registers */
#define SDMA_INTR_CAUSE 0x0000
......@@ -308,11 +307,11 @@ struct mpsc_port_info *mpsc_device_remove(int index);
* Define how this driver is known to the outside (we've been assigned a
* range on the "Low-density serial ports" major).
*/
#define MPSC_MAJOR 204
#define MPSC_MINOR_START 44
#define MPSC_DRIVER_NAME "MPSC"
#define MPSC_DEV_NAME "ttyMM"
#define MPSC_VERSION "1.00"
#define MPSC_MAJOR 204
#define MPSC_MINOR_START 44
#define MPSC_DRIVER_NAME "MPSC"
#define MPSC_DEV_NAME "ttyMM"
#define MPSC_VERSION "1.00"
static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
static struct mpsc_shared_regs mpsc_shared_regs;
......@@ -328,8 +327,7 @@ static void mpsc_release_port(struct uart_port *port);
*
******************************************************************************
*/
static void
mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
{
u32 v;
......@@ -345,11 +343,9 @@ mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
pi->brg_base + BRG_BTR);
return;
}
static void
mpsc_brg_enable(struct mpsc_port_info *pi)
static void mpsc_brg_enable(struct mpsc_port_info *pi)
{
u32 v;
......@@ -359,11 +355,9 @@ mpsc_brg_enable(struct mpsc_port_info *pi)
if (pi->mirror_regs)
pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR);
return;
}
static void
mpsc_brg_disable(struct mpsc_port_info *pi)
static void mpsc_brg_disable(struct mpsc_port_info *pi)
{
u32 v;
......@@ -373,21 +367,19 @@ mpsc_brg_disable(struct mpsc_port_info *pi)
if (pi->mirror_regs)
pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR);
return;
}
static inline void
mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
/*
* To set the baud, we adjust the CDV field in the BRG_BCR reg.
* From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
* However, the input clock is divided by 16 in the MPSC b/c of how
* 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
* calculation by 16 to account for that. So the real calculation
* that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
*/
static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
{
/*
* To set the baud, we adjust the CDV field in the BRG_BCR reg.
* From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
* However, the input clock is divided by 16 in the MPSC b/c of how
* 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
* calculation by 16 to account for that. So the real calculation
* that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
*/
u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
u32 v;
......@@ -399,8 +391,6 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR);
mpsc_brg_enable(pi);
return;
}
/*
......@@ -411,13 +401,12 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
******************************************************************************
*/
static void
mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
{
u32 v;
pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
pi->port.line, burst_size);
pi->port.line, burst_size);
burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
......@@ -432,11 +421,9 @@ mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
pi->sdma_base + SDMA_SDC);
return;
}
static void
mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
{
pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
burst_size);
......@@ -444,11 +431,9 @@ mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
pi->sdma_base + SDMA_SDC);
mpsc_sdma_burstsize(pi, burst_size);
return;
}
static inline u32
mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
{
u32 old, v;
......@@ -471,15 +456,14 @@ mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
return old & 0xf;
}
static inline void
mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
{
u32 v;
pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
: readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
mask &= 0xf;
if (pi->port.line)
......@@ -489,41 +473,35 @@ mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
if (pi->mirror_regs)
pi->shared_regs->SDMA_INTR_MASK_m = v;
writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
return;
}
static inline void
mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
{
pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
if (pi->mirror_regs)
pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE +
pi->port.line);
return;
writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
+ pi->port.line);
}
static inline void
mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
struct mpsc_rx_desc *rxre_p)
{
pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
pi->port.line, (u32) rxre_p);
pi->port.line, (u32)rxre_p);
writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
return;
}
static inline void
mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
struct mpsc_tx_desc *txre_p)
{
writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
return;
}
static inline void
mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
{
u32 v;
......@@ -535,46 +513,40 @@ mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
wmb();
writel(v, pi->sdma_base + SDMA_SDCM);
wmb();
return;
}
static inline uint
mpsc_sdma_tx_active(struct mpsc_port_info *pi)
static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
{
return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
}
static inline void
mpsc_sdma_start_tx(struct mpsc_port_info *pi)
static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
{
struct mpsc_tx_desc *txre, *txre_p;
/* If tx isn't running & there's a desc ready to go, start it */
if (!mpsc_sdma_tx_active(pi)) {
txre = (struct mpsc_tx_desc *)(pi->txr +
(pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
txre = (struct mpsc_tx_desc *)(pi->txr
+ (pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)txre,
(ulong)txre + MPSC_TXRE_SIZE);
(ulong)txre + MPSC_TXRE_SIZE);
#endif
if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
(pi->txr_tail *
MPSC_TXRE_SIZE));
txre_p = (struct mpsc_tx_desc *)
(pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
mpsc_sdma_set_tx_ring(pi, txre_p);
mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
}
}
return;
}
static inline void
mpsc_sdma_stop(struct mpsc_port_info *pi)
static void mpsc_sdma_stop(struct mpsc_port_info *pi)
{
pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
......@@ -589,8 +561,6 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
/* Disable interrupts */
mpsc_sdma_intr_mask(pi, 0xf);
mpsc_sdma_intr_ack(pi);
return;
}
/*
......@@ -601,8 +571,7 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
******************************************************************************
*/
static void
mpsc_hw_init(struct mpsc_port_info *pi)
static void mpsc_hw_init(struct mpsc_port_info *pi)
{
u32 v;
......@@ -624,8 +593,7 @@ mpsc_hw_init(struct mpsc_port_info *pi)
v = (v & ~0xf0f) | 0x100;
pi->shared_regs->MPSC_TCRR_m = v;
writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
}
else {
} else {
v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
v &= ~0x1c7;
writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
......@@ -642,7 +610,7 @@ mpsc_hw_init(struct mpsc_port_info *pi)
/* Put MPSC in UART mode & enabel Tx/Rx egines */
writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
/* No preamble, 16x divider, low-latency, */
/* No preamble, 16x divider, low-latency, */
writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
if (pi->mirror_regs) {
......@@ -659,12 +627,9 @@ mpsc_hw_init(struct mpsc_port_info *pi)
writel(0, pi->mpsc_base + MPSC_CHR_8);
writel(0, pi->mpsc_base + MPSC_CHR_9);
writel(0, pi->mpsc_base + MPSC_CHR_10);
return;
}
static inline void
mpsc_enter_hunt(struct mpsc_port_info *pi)
static void mpsc_enter_hunt(struct mpsc_port_info *pi)
{
pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
......@@ -673,20 +638,16 @@ mpsc_enter_hunt(struct mpsc_port_info *pi)
pi->mpsc_base + MPSC_CHR_2);
/* Erratum prevents reading CHR_2 so just delay for a while */
udelay(100);
}
else {
} else {
writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
pi->mpsc_base + MPSC_CHR_2);
pi->mpsc_base + MPSC_CHR_2);
while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
udelay(10);
}
return;
}
static inline void
mpsc_freeze(struct mpsc_port_info *pi)
static void mpsc_freeze(struct mpsc_port_info *pi)
{
u32 v;
......@@ -699,11 +660,9 @@ mpsc_freeze(struct mpsc_port_info *pi)
if (pi->mirror_regs)
pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_unfreeze(struct mpsc_port_info *pi)
static void mpsc_unfreeze(struct mpsc_port_info *pi)
{
u32 v;
......@@ -716,11 +675,9 @@ mpsc_unfreeze(struct mpsc_port_info *pi)
writel(v, pi->mpsc_base + MPSC_MPCR);
pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
return;
}
static inline void
mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
{
u32 v;
......@@ -733,11 +690,9 @@ mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
if (pi->mirror_regs)
pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
{
u32 v;
......@@ -752,11 +707,9 @@ mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
if (pi->mirror_regs)
pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
{
u32 v;
......@@ -771,7 +724,6 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
if (pi->mirror_regs)
pi->MPSC_CHR_2_m = v;
writel(v, pi->mpsc_base + MPSC_CHR_2);
return;
}
/*
......@@ -782,8 +734,7 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
******************************************************************************
*/
static void
mpsc_init_hw(struct mpsc_port_info *pi)
static void mpsc_init_hw(struct mpsc_port_info *pi)
{
pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
......@@ -792,12 +743,9 @@ mpsc_init_hw(struct mpsc_port_info *pi)
mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
mpsc_sdma_stop(pi);
mpsc_hw_init(pi);
return;
}
static int
mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
{
int rc = 0;
......@@ -808,11 +756,10 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
if (!dma_supported(pi->port.dev, 0xffffffff)) {
printk(KERN_ERR "MPSC: Inadequate DMA support\n");
rc = -ENXIO;
}
else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
== NULL) {
} else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
MPSC_DMA_ALLOC_SIZE,
&pi->dma_region_p, GFP_KERNEL))
== NULL) {
printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
rc = -ENOMEM;
}
......@@ -821,23 +768,19 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
return rc;
}
static void
mpsc_free_ring_mem(struct mpsc_port_info *pi)
static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
{
pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
if (pi->dma_region) {
dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
pi->dma_region, pi->dma_region_p);
pi->dma_region, pi->dma_region_p);
pi->dma_region = NULL;
pi->dma_region_p = (dma_addr_t) NULL;
pi->dma_region_p = (dma_addr_t)NULL;
}
return;
}
static void
mpsc_init_rings(struct mpsc_port_info *pi)
static void mpsc_init_rings(struct mpsc_port_info *pi)
{
struct mpsc_rx_desc *rxre;
struct mpsc_tx_desc *txre;
......@@ -855,8 +798,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
* Descriptors & buffers are multiples of cacheline size and must be
* cacheline aligned.
*/
dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
/*
* Partition dma region into rx ring descriptor, rx buffers,
......@@ -867,8 +810,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
dp += MPSC_RXR_SIZE;
dp_p += MPSC_RXR_SIZE;
pi->rxb = (u8 *) dp;
pi->rxb_p = (u8 *) dp_p;
pi->rxb = (u8 *)dp;
pi->rxb_p = (u8 *)dp_p;
dp += MPSC_RXB_SIZE;
dp_p += MPSC_RXB_SIZE;
......@@ -879,8 +822,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
dp += MPSC_TXR_SIZE;
dp_p += MPSC_TXR_SIZE;
pi->txb = (u8 *) dp;
pi->txb_p = (u8 *) dp_p;
pi->txb = (u8 *)dp;
pi->txb_p = (u8 *)dp_p;
pi->txr_head = 0;
pi->txr_tail = 0;
......@@ -896,10 +839,9 @@ mpsc_init_rings(struct mpsc_port_info *pi)
rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
rxre->bytecnt = cpu_to_be16(0);
rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
SDMA_DESC_CMDSTAT_EI |
SDMA_DESC_CMDSTAT_F |
SDMA_DESC_CMDSTAT_L);
rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
| SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
| SDMA_DESC_CMDSTAT_L);
rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
rxre->buf_ptr = cpu_to_be32(bp_p);
......@@ -929,19 +871,19 @@ mpsc_init_rings(struct mpsc_port_info *pi)
}
txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
DMA_BIDIRECTIONAL);
dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)pi->dma_region,
(ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
(ulong)pi->dma_region
+ MPSC_DMA_ALLOC_SIZE);
#endif
return;
}
static void
mpsc_uninit_rings(struct mpsc_port_info *pi)
static void mpsc_uninit_rings(struct mpsc_port_info *pi)
{
pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
......@@ -959,12 +901,9 @@ mpsc_uninit_rings(struct mpsc_port_info *pi)
pi->txb_p = NULL;
pi->txr_head = 0;
pi->txr_tail = 0;
return;
}
static int
mpsc_make_ready(struct mpsc_port_info *pi)
static int mpsc_make_ready(struct mpsc_port_info *pi)
{
int rc;
......@@ -989,8 +928,7 @@ mpsc_make_ready(struct mpsc_port_info *pi)
******************************************************************************
*/
static inline int
mpsc_rx_intr(struct mpsc_port_info *pi)
static int mpsc_rx_intr(struct mpsc_port_info *pi)
{
struct mpsc_rx_desc *rxre;
struct tty_struct *tty = pi->port.info->tty;
......@@ -1003,21 +941,24 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)rxre,
(ulong)rxre + MPSC_RXRE_SIZE);
(ulong)rxre + MPSC_RXRE_SIZE);
#endif
/*
* Loop through Rx descriptors handling ones that have been completed.
*/
while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
& SDMA_DESC_CMDSTAT_O)) {
bytes_in = be16_to_cpu(rxre->bytecnt);
/* Following use of tty struct directly is deprecated */
if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
if (unlikely(tty_buffer_request_room(tty, bytes_in)
< bytes_in)) {
if (tty->low_latency)
tty_flip_buffer_push(tty);
/*
......@@ -1027,11 +968,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
}
bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)bp,
(ulong)bp + MPSC_RXBE_SIZE);
(ulong)bp + MPSC_RXBE_SIZE);
#endif
/*
......@@ -1042,8 +984,9 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
* we'll assume there is no data in the buffer.
* If there is...it gets lost.
*/
if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
| SDMA_DESC_CMDSTAT_FR
| SDMA_DESC_CMDSTAT_OR))) {