Commit 2c1cfb2d authored by Sam Ravnborg's avatar Sam Ravnborg Committed by David S. Miller
Browse files

sparc32: drop sun4c support



Machines with sun4c support are very rare these days, and noone
is using them for any practical purposes.
The sun4c support has been know broken for quite some time too.

So rather than trying to keep it up-to-date, lets get rid of it.
This allows us to do some very welcome cleanup of sparc32 support.

Updated the former sun4c specifc nmi (which was also used
for sun4m UP) to be a generic UP NMI.
Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent aa6f0790
......@@ -80,16 +80,6 @@
#define TRAP_ENTRY_INTERRUPT(int_level) \
mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
/* NMI's (Non Maskable Interrupts) are special, you can't keep them
* from coming in, and basically if you get one, the shows over. ;(
* On the sun4c they are usually asynchronous memory errors, on the
* the sun4m they could be either due to mem errors or a software
* initiated interrupt from the prom/kern on an SMP box saying "I
* command you to do CPU tricks, read your mailbox for more info."
*/
#define NMI_TRAP \
rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
/* Window overflows/underflows are special and we need to try to be as
* efficient as possible here....
*/
......
......@@ -105,14 +105,6 @@ extern void prom_write(const char *buf, unsigned int len);
extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
int context, char *program_counter);
/* Sun4/sun4c specific memory-management startup hook. */
/* Map the passed segment in the given context at the passed
* virtual address.
*/
extern void prom_putsegment(int context, unsigned long virt_addr,
int physical_segment);
/* Initialize the memory lists based upon the prom version. */
void prom_meminit(void);
......
......@@ -28,7 +28,7 @@ obj-y += traps_$(BITS).o
# IRQ
obj-y += irq_$(BITS).o
obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4c_irq.o sun4d_irq.o
obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4d_irq.o
obj-y += process_$(BITS).o
obj-y += signal_$(BITS).o
......
......@@ -317,8 +317,8 @@ maybe_smp4m_msg_out:
RESTORE_ALL
.align 4
.globl linux_trap_ipi15_sun4m
linux_trap_ipi15_sun4m:
.globl linux_trap_ipi15
linux_trap_ipi15:
SAVE_ALL
sethi %hi(0x80000000), %o2
GET_PROCESSOR4M_ID(o0)
......@@ -760,20 +760,12 @@ setcc_trap_handler:
jmp %l2 ! advance over trap instruction
rett %l2 + 0x4 ! like this...
#ifndef CONFIG_SMP
.align 4
.globl linux_trap_nmi_sun4c
linux_trap_nmi_sun4c:
.globl linux_trap_ipi15
linux_trap_ipi15:
SAVE_ALL
/* Ugh, we need to clear the IRQ line. This is now
* a very sun4c specific trap handler...
*/
sethi %hi(interrupt_enable), %l5
ld [%l5 + %lo(interrupt_enable)], %l5
ldub [%l5], %l6
andn %l6, INTS_ENAB, %l6
stb %l6, [%l5]
/* Now it is safe to re-enable traps without recursion. */
or %l0, PSR_PIL, %l0
wr %l0, PSR_ET, %psr
......@@ -797,6 +789,8 @@ linux_trap_nmi_sun4c:
RESTORE_ALL
#endif /* CONFIG_SMP */
.align 4
.globl invalid_segment_patch1_ff
.globl invalid_segment_patch2_ff
......
......@@ -111,11 +111,8 @@ t_irq12:TRAP_ENTRY_INTERRUPT(12) /* IRQ Zilog serial chip */
t_irq13:TRAP_ENTRY_INTERRUPT(13) /* IRQ Audio Intr. */
t_irq14:TRAP_ENTRY_INTERRUPT(14) /* IRQ Timer #2 */
.globl t_nmi
#ifndef CONFIG_SMP
t_nmi: NMI_TRAP /* Level 15 (NMI) */
#else
t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
#endif
t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15)
t_racc: TRAP_ENTRY(0x20, do_reg_access) /* General Register Access Error */
t_iacce:BAD_TRAP(0x21) /* Instr Access Error */
t_bad22:BAD_TRAP(0x22) BAD_TRAP(0x23)
......
......@@ -346,11 +346,6 @@ void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs)
void __init init_IRQ(void)
{
switch (sparc_cpu_model) {
case sun4c:
case sun4:
sun4c_init_IRQ();
break;
case sun4m:
pcic_probe();
if (pcic_present())
......
......@@ -43,9 +43,6 @@ extern spinlock_t irq_action_lock;
extern void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs);
extern void init_IRQ(void);
/* sun4c_irq.c */
extern void sun4c_init_IRQ(void);
/* sun4m_irq.c */
extern void sun4m_init_IRQ(void);
extern void sun4m_unmask_profile_irq(void);
......
......@@ -100,7 +100,7 @@ void cpu_idle(void)
printk("kernel faults / second = %ld\n", fps);
#endif
if (fps >= SUN4C_FAULT_HIGH) {
sun4c_grow_kernel_ring();
/*sun4c_grow_kernel_ring();*/
}
}
local_irq_enable();
......
/*
* sun4c irq support
*
* djhr: Hacked out of irq.c into a CPU dependent version.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
*/
#include <linux/init.h>
#include <asm/oplib.h>
#include <asm/timer.h>
#include <asm/irq.h>
#include <asm/io.h>
#include "irq.h"
/* Sun4c interrupts are typically laid out as follows:
*
* 1 - Software interrupt, SBUS level 1
* 2 - SBUS level 2
* 3 - ESP SCSI, SBUS level 3
* 4 - Software interrupt
* 5 - Lance ethernet, SBUS level 4
* 6 - Software interrupt
* 7 - Graphics card, SBUS level 5
* 8 - SBUS level 6
* 9 - SBUS level 7
* 10 - Counter timer
* 11 - Floppy
* 12 - Zilog uart
* 13 - CS4231 audio
* 14 - Profiling timer
* 15 - NMI
*
* The interrupt enable bits in the interrupt mask register are
* really only used to enable/disable the timer interrupts, and
* for signalling software interrupts. There is also a master
* interrupt enable bit in this register.
*
* Interrupts are enabled by setting the SUN4C_INT_* bits, they
* are disabled by clearing those bits.
*/
/*
* Bit field defines for the interrupt registers on various
* Sparc machines.
*/
/* The sun4c interrupt register. */
#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
/*
* Pointer to the interrupt enable byte
* Used by entry.S
*/
unsigned char __iomem *interrupt_enable;
static void sun4c_mask_irq(struct irq_data *data)
{
unsigned long mask = (unsigned long)data->chip_data;
if (mask) {
unsigned long flags;
local_irq_save(flags);
mask = sbus_readb(interrupt_enable) & ~mask;
sbus_writeb(mask, interrupt_enable);
local_irq_restore(flags);
}
}
static void sun4c_unmask_irq(struct irq_data *data)
{
unsigned long mask = (unsigned long)data->chip_data;
if (mask) {
unsigned long flags;
local_irq_save(flags);
mask = sbus_readb(interrupt_enable) | mask;
sbus_writeb(mask, interrupt_enable);
local_irq_restore(flags);
}
}
static unsigned int sun4c_startup_irq(struct irq_data *data)
{
irq_link(data->irq);
sun4c_unmask_irq(data);
return 0;
}
static void sun4c_shutdown_irq(struct irq_data *data)
{
sun4c_mask_irq(data);
irq_unlink(data->irq);
}
static struct irq_chip sun4c_irq = {
.name = "sun4c",
.irq_startup = sun4c_startup_irq,
.irq_shutdown = sun4c_shutdown_irq,
.irq_mask = sun4c_mask_irq,
.irq_unmask = sun4c_unmask_irq,
};
static unsigned int sun4c_build_device_irq(struct platform_device *op,
unsigned int real_irq)
{
unsigned int irq;
if (real_irq >= 16) {
prom_printf("Bogus sun4c IRQ %u\n", real_irq);
prom_halt();
}
irq = irq_alloc(real_irq, real_irq);
if (irq) {
unsigned long mask = 0UL;
switch (real_irq) {
case 1:
mask = SUN4C_INT_E1;
break;
case 8:
mask = SUN4C_INT_E8;
break;
case 10:
mask = SUN4C_INT_E10;
break;
case 14:
mask = SUN4C_INT_E14;
break;
default:
/* All the rest are either always enabled,
* or are for signalling software interrupts.
*/
break;
}
irq_set_chip_and_handler_name(irq, &sun4c_irq,
handle_level_irq, "level");
irq_set_chip_data(irq, (void *)mask);
}
return irq;
}
struct sun4c_timer_info {
u32 l10_count;
u32 l10_limit;
u32 l14_count;
u32 l14_limit;
};
static struct sun4c_timer_info __iomem *sun4c_timers;
static void sun4c_clear_clock_irq(void)
{
sbus_readl(&sun4c_timers->l10_limit);
}
static void sun4c_load_profile_irq(int cpu, unsigned int limit)
{
/* Errm.. not sure how to do this.. */
}
static void __init sun4c_init_timers(void)
{
const struct linux_prom_irqs *prom_irqs;
struct device_node *dp;
unsigned int irq;
const u32 *addr;
int err;
dp = of_find_node_by_name(NULL, "counter-timer");
if (!dp) {
prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
prom_halt();
}
addr = of_get_property(dp, "address", NULL);
if (!addr) {
prom_printf("sun4c_init_timers: No address property\n");
prom_halt();
}
sun4c_timers = (void __iomem *) (unsigned long) addr[0];
prom_irqs = of_get_property(dp, "intr", NULL);
of_node_put(dp);
if (!prom_irqs) {
prom_printf("sun4c_init_timers: No intr property\n");
prom_halt();
}
/* Have the level 10 timer tick at 100HZ. We don't touch the
* level 14 timer limit since we are letting the prom handle
* them until we have a real console driver so L1-A works.
*/
sparc_config.cs_period = SBUS_CLOCK_RATE / HZ;
sparc_config.features |=
FEAT_L10_CLOCKSOURCE | FEAT_L10_CLOCKEVENT;
sbus_writel(timer_value(sparc_config.cs_period),
&sun4c_timers->l10_limit);
master_l10_counter = &sun4c_timers->l10_count;
irq = sun4c_build_device_irq(NULL, prom_irqs[0].pri);
err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
if (err) {
prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
prom_halt();
}
/* disable timer interrupt */
sun4c_mask_irq(irq_get_irq_data(irq));
}
#ifdef CONFIG_SMP
static void sun4c_nop(void)
{
}
#endif
void __init sun4c_init_IRQ(void)
{
struct device_node *dp;
const u32 *addr;
dp = of_find_node_by_name(NULL, "interrupt-enable");
if (!dp) {
prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
prom_halt();
}
addr = of_get_property(dp, "address", NULL);
of_node_put(dp);
if (!addr) {
prom_printf("sun4c_init_IRQ: No address property\n");
prom_halt();
}
interrupt_enable = (void __iomem *) (unsigned long) addr[0];
BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
sparc_config.init_timers = sun4c_init_timers;
sparc_config.build_device_irq = sun4c_build_device_irq;
sparc_config.clock_rate = SBUS_CLOCK_RATE;
#ifdef CONFIG_SMP
BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
#endif
sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
/* Cannot enable interrupts until OBP ticker is disabled. */
}
......@@ -18,8 +18,4 @@ obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
# Only used by sparc32
obj-$(CONFIG_HIGHMEM) += highmem.o
ifdef CONFIG_SMP
obj-$(CONFIG_SPARC32) += nosun4c.o
else
obj-$(CONFIG_SPARC32) += sun4c.o
endif
This diff is collapsed.
......@@ -10,7 +10,6 @@ lib-$(CONFIG_SPARC32) += memory.o
lib-y += misc_$(BITS).o
lib-$(CONFIG_SPARC32) += mp.o
lib-$(CONFIG_SPARC32) += ranges.o
lib-$(CONFIG_SPARC32) += segment.o
lib-y += console_$(BITS).o
lib-y += printf.o
lib-y += tree_$(BITS).o
......
/*
* segment.c: Prom routine to map segments in other contexts before
* a standalone is completely mapped. This is for sun4 and
* sun4c architectures only.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
extern void restore_current(void);
/* Set physical segment 'segment' at virtual address 'vaddr' in
* context 'ctx'.
*/
void
prom_putsegment(int ctx, unsigned long vaddr, int segment)
{
unsigned long flags;
spin_lock_irqsave(&prom_lock, flags);
(*(romvec->pv_setctxt))(ctx, (char *) vaddr, segment);
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);
}
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment