Commit 25d7a600 authored by Oskar Schirmer's avatar Oskar Schirmer Committed by Thomas Gleixner
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arm: tcc8k: Avoid reading clock register twice



There is no reason why in case of PLL2 the configuration register
should be read twice, while for PLL0/1 using the value previously read
is used. Do the same for PLL2.
Signed-off-by: default avatarOskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent fe03a9f7
......@@ -199,7 +199,7 @@ static unsigned long get_rate_pll_div(int pll)
addr = CKC_BASE + CLKDIVC1_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC1_P2E)
div = __raw_readl(addr) & 0x3f;
div = reg & 0x3f;
break;
}
return get_rate_pll(pll) / (div + 1);
......
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