Commit 1e7d06ba authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next



Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2015-01-16

This series contains updates to i40e and i40evf.

This series is a little bit larger than normal because two of the patches are
version bumps.

Shannon provides tweaks to i40e and i40evf to keep the firmware, software
and silicon validation in line together by removing unused and
deprecated code, adding define for iSCSI and fix queue mask size.  Fix
i40e so we do not give up in the reset/rebuild process if DCB setup
fails, just handle it the same as in the probe setup.  Cleans up PTP
log messages by removing the use of __func__ as we are not using that
any longer and removes the netdev name, since that can change and can
be misleading.  Adds struct size checks to indirect and command
structs that were left out previously.  Added admin queue API updates
(LLDP control, OEM OCSD and OCBB commands).

Kevin increases ASQ timeout for scenarios with multi-function devices.

Carolyn fixes a problem where the interrupts descriptions from the MSIx
configuration were truncating the needed bus info, which makes it hard
to distinguish configurations from port to port.  Increased the string
buffer size in order to allow the full data to be displayed.

Sravanthi cleans up the dump stats string from debugfs.

Jacob updates i40e to only enable the PTP interrupt in PFs which have PTP
enabled, instead of blindly enabling the PTP interrupt flags for all PFs.
Also updated i40e so that we do not do Tx or Rx timestamps if we do not
have PTP enabled.  Added the same check against pf->ptp_rx as we have
in Rx timestamp code path because it is possible that the user can
configure only Tx hardware timestamping so we do not want to check for
Rx timestamp hang since the software won't be handling them.

Neerav updates the driver to disable firmware LLDP agent for NICs with
a firmware version lower than v4.3 and added a message when this happens.
Adds parsing and reporting of iSCSI capability for a given device or
function, as well as adding support for iSCSI partition type with DCB
in NPAR mode.

v2:
 - Dropped patch 10 "i40e: clean up PTP log messages" based on feedback
   from David Laight and David Miller
 - Split up the original patch 13 "i40e: AQ API updates for new commands"
   into 2 patches (now #12 & #13) based on feedback from Or Gerlitz
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 93d62ef9 300c34c1
...@@ -92,6 +92,7 @@ ...@@ -92,6 +92,7 @@
#define I40E_MAX_USER_PRIORITY 8 #define I40E_MAX_USER_PRIORITY 8
#define I40E_DEFAULT_MSG_ENABLE 4 #define I40E_DEFAULT_MSG_ENABLE 4
#define I40E_QUEUE_WAIT_RETRY_LIMIT 10 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 9)
#define I40E_NVM_VERSION_LO_SHIFT 0 #define I40E_NVM_VERSION_LO_SHIFT 0
#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
...@@ -268,7 +269,7 @@ struct i40e_pf { ...@@ -268,7 +269,7 @@ struct i40e_pf {
u16 rx_itr_default; u16 rx_itr_default;
u16 tx_itr_default; u16 tx_itr_default;
u16 msg_enable; u16 msg_enable;
char misc_int_name[IFNAMSIZ + 9]; char int_name[I40E_INT_NAME_STR_LEN];
u16 adminq_work_limit; /* num of admin receive queue desc to process */ u16 adminq_work_limit; /* num of admin receive queue desc to process */
unsigned long service_timer_period; unsigned long service_timer_period;
unsigned long service_timer_previous; unsigned long service_timer_previous;
...@@ -524,7 +525,7 @@ struct i40e_q_vector { ...@@ -524,7 +525,7 @@ struct i40e_q_vector {
cpumask_t affinity_mask; cpumask_t affinity_mask;
struct rcu_head rcu; /* to avoid race with update stats on free */ struct rcu_head rcu; /* to avoid race with update stats on free */
char name[IFNAMSIZ + 9]; char name[I40E_INT_NAME_STR_LEN];
} ____cacheline_internodealigned_in_smp; } ____cacheline_internodealigned_in_smp;
/* lan device */ /* lan device */
......
...@@ -148,7 +148,7 @@ static inline int i40e_aq_rc_to_posix(u32 aq_ret, u16 aq_rc) ...@@ -148,7 +148,7 @@ static inline int i40e_aq_rc_to_posix(u32 aq_ret, u16 aq_rc)
/* general information */ /* general information */
#define I40E_AQ_LARGE_BUF 512 #define I40E_AQ_LARGE_BUF 512
#define I40E_ASQ_CMD_TIMEOUT 100 /* msecs */ #define I40E_ASQ_CMD_TIMEOUT 250 /* msecs */
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
u16 opcode); u16 opcode);
......
...@@ -256,6 +256,8 @@ enum i40e_admin_queue_opc { ...@@ -256,6 +256,8 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_lldp_stop = 0x0A05, i40e_aqc_opc_lldp_stop = 0x0A05,
i40e_aqc_opc_lldp_start = 0x0A06, i40e_aqc_opc_lldp_start = 0x0A06,
i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
/* Tunnel commands */ /* Tunnel commands */
i40e_aqc_opc_add_udp_tunnel = 0x0B00, i40e_aqc_opc_add_udp_tunnel = 0x0B00,
...@@ -268,6 +270,8 @@ enum i40e_admin_queue_opc { ...@@ -268,6 +270,8 @@ enum i40e_admin_queue_opc {
/* OEM commands */ /* OEM commands */
i40e_aqc_opc_oem_parameter_change = 0xFE00, i40e_aqc_opc_oem_parameter_change = 0xFE00,
i40e_aqc_opc_oem_device_status_change = 0xFE01, i40e_aqc_opc_oem_device_status_change = 0xFE01,
i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
/* debug commands */ /* debug commands */
i40e_aqc_opc_debug_get_deviceid = 0xFF00, i40e_aqc_opc_debug_get_deviceid = 0xFF00,
...@@ -276,7 +280,6 @@ enum i40e_admin_queue_opc { ...@@ -276,7 +280,6 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_debug_write_reg = 0xFF04, i40e_aqc_opc_debug_write_reg = 0xFF04,
i40e_aqc_opc_debug_modify_reg = 0xFF07, i40e_aqc_opc_debug_modify_reg = 0xFF07,
i40e_aqc_opc_debug_dump_internals = 0xFF08, i40e_aqc_opc_debug_dump_internals = 0xFF08,
i40e_aqc_opc_debug_modify_internals = 0xFF09,
}; };
/* command structures and indirect data structures */ /* command structures and indirect data structures */
...@@ -410,6 +413,7 @@ struct i40e_aqc_list_capabilities_element_resp { ...@@ -410,6 +413,7 @@ struct i40e_aqc_list_capabilities_element_resp {
#define I40E_AQ_CAP_ID_VSI 0x0017 #define I40E_AQ_CAP_ID_VSI 0x0017
#define I40E_AQ_CAP_ID_DCB 0x0018 #define I40E_AQ_CAP_ID_DCB 0x0018
#define I40E_AQ_CAP_ID_FCOE 0x0021 #define I40E_AQ_CAP_ID_FCOE 0x0021
#define I40E_AQ_CAP_ID_ISCSI 0x0022
#define I40E_AQ_CAP_ID_RSS 0x0040 #define I40E_AQ_CAP_ID_RSS 0x0040
#define I40E_AQ_CAP_ID_RXQ 0x0041 #define I40E_AQ_CAP_ID_RXQ 0x0041
#define I40E_AQ_CAP_ID_TXQ 0x0042 #define I40E_AQ_CAP_ID_TXQ 0x0042
...@@ -454,8 +458,11 @@ struct i40e_aqc_arp_proxy_data { ...@@ -454,8 +458,11 @@ struct i40e_aqc_arp_proxy_data {
__le32 pfpm_proxyfc; __le32 pfpm_proxyfc;
__le32 ip_addr; __le32 ip_addr;
u8 mac_addr[6]; u8 mac_addr[6];
u8 reserved[2];
}; };
I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
/* Set NS Proxy Table Entry Command (indirect 0x0105) */ /* Set NS Proxy Table Entry Command (indirect 0x0105) */
struct i40e_aqc_ns_proxy_data { struct i40e_aqc_ns_proxy_data {
__le16 table_idx_mac_addr_0; __le16 table_idx_mac_addr_0;
...@@ -481,6 +488,8 @@ struct i40e_aqc_ns_proxy_data { ...@@ -481,6 +488,8 @@ struct i40e_aqc_ns_proxy_data {
u8 ipv6_addr_1[16]; u8 ipv6_addr_1[16];
}; };
I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
/* Manage LAA Command (0x0106) - obsolete */ /* Manage LAA Command (0x0106) - obsolete */
struct i40e_aqc_mng_laa { struct i40e_aqc_mng_laa {
__le16 command_flags; __le16 command_flags;
...@@ -491,6 +500,8 @@ struct i40e_aqc_mng_laa { ...@@ -491,6 +500,8 @@ struct i40e_aqc_mng_laa {
u8 reserved2[6]; u8 reserved2[6];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
/* Manage MAC Address Read Command (indirect 0x0107) */ /* Manage MAC Address Read Command (indirect 0x0107) */
struct i40e_aqc_mac_address_read { struct i40e_aqc_mac_address_read {
__le16 command_flags; __le16 command_flags;
...@@ -562,6 +573,8 @@ struct i40e_aqc_get_switch_config_header_resp { ...@@ -562,6 +573,8 @@ struct i40e_aqc_get_switch_config_header_resp {
u8 reserved[12]; u8 reserved[12];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
struct i40e_aqc_switch_config_element_resp { struct i40e_aqc_switch_config_element_resp {
u8 element_type; u8 element_type;
#define I40E_AQ_SW_ELEM_TYPE_MAC 1 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
...@@ -587,6 +600,8 @@ struct i40e_aqc_switch_config_element_resp { ...@@ -587,6 +600,8 @@ struct i40e_aqc_switch_config_element_resp {
__le16 element_info; __le16 element_info;
}; };
I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
/* Get Switch Configuration (indirect 0x0200) /* Get Switch Configuration (indirect 0x0200)
* an array of elements are returned in the response buffer * an array of elements are returned in the response buffer
* the first in the array is the header, remainder are elements * the first in the array is the header, remainder are elements
...@@ -596,6 +611,8 @@ struct i40e_aqc_get_switch_config_resp { ...@@ -596,6 +611,8 @@ struct i40e_aqc_get_switch_config_resp {
struct i40e_aqc_switch_config_element_resp element[1]; struct i40e_aqc_switch_config_element_resp element[1];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
/* Add Statistics (direct 0x0201) /* Add Statistics (direct 0x0201)
* Remove Statistics (direct 0x0202) * Remove Statistics (direct 0x0202)
*/ */
...@@ -661,6 +678,8 @@ struct i40e_aqc_switch_resource_alloc_element_resp { ...@@ -661,6 +678,8 @@ struct i40e_aqc_switch_resource_alloc_element_resp {
u8 reserved2[6]; u8 reserved2[6];
}; };
I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
/* Add VSI (indirect 0x0210) /* Add VSI (indirect 0x0210)
* this indirect command uses struct i40e_aqc_vsi_properties_data * this indirect command uses struct i40e_aqc_vsi_properties_data
* as the indirect buffer (128 bytes) * as the indirect buffer (128 bytes)
...@@ -1092,6 +1111,8 @@ struct i40e_aqc_remove_tag { ...@@ -1092,6 +1111,8 @@ struct i40e_aqc_remove_tag {
u8 reserved[12]; u8 reserved[12];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
/* Add multicast E-Tag (direct 0x0257) /* Add multicast E-Tag (direct 0x0257)
* del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
* and no external data * and no external data
...@@ -1207,7 +1228,7 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { ...@@ -1207,7 +1228,7 @@ struct i40e_aqc_add_remove_cloud_filters_element_data {
} ipaddr; } ipaddr;
__le16 flags; __le16 flags;
#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
I40E_AQC_ADD_CLOUD_FILTER_SHIFT) I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
/* 0x0000 reserved */ /* 0x0000 reserved */
#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
...@@ -1240,7 +1261,7 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { ...@@ -1240,7 +1261,7 @@ struct i40e_aqc_add_remove_cloud_filters_element_data {
u8 reserved[4]; u8 reserved[4];
__le16 queue_number; __le16 queue_number;
#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
u8 reserved2[14]; u8 reserved2[14];
/* response section */ /* response section */
...@@ -1359,6 +1380,8 @@ struct i40e_aqc_configure_vsi_ets_sla_bw_data { ...@@ -1359,6 +1380,8 @@ struct i40e_aqc_configure_vsi_ets_sla_bw_data {
u8 reserved1[28]; u8 reserved1[28];
}; };
I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
* responds with i40e_aqc_qs_handles_resp * responds with i40e_aqc_qs_handles_resp
*/ */
...@@ -1370,6 +1393,8 @@ struct i40e_aqc_configure_vsi_tc_bw_data { ...@@ -1370,6 +1393,8 @@ struct i40e_aqc_configure_vsi_tc_bw_data {
__le16 qs_handles[8]; __le16 qs_handles[8];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
/* Query vsi bw configuration (indirect 0x0408) */ /* Query vsi bw configuration (indirect 0x0408) */
struct i40e_aqc_query_vsi_bw_config_resp { struct i40e_aqc_query_vsi_bw_config_resp {
u8 tc_valid_bits; u8 tc_valid_bits;
...@@ -1383,6 +1408,8 @@ struct i40e_aqc_query_vsi_bw_config_resp { ...@@ -1383,6 +1408,8 @@ struct i40e_aqc_query_vsi_bw_config_resp {
u8 reserved3[23]; u8 reserved3[23];
}; };
I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
struct i40e_aqc_query_vsi_ets_sla_config_resp { struct i40e_aqc_query_vsi_ets_sla_config_resp {
u8 tc_valid_bits; u8 tc_valid_bits;
...@@ -1394,6 +1421,8 @@ struct i40e_aqc_query_vsi_ets_sla_config_resp { ...@@ -1394,6 +1421,8 @@ struct i40e_aqc_query_vsi_ets_sla_config_resp {
__le16 tc_bw_max[2]; __le16 tc_bw_max[2];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
struct i40e_aqc_configure_switching_comp_bw_limit { struct i40e_aqc_configure_switching_comp_bw_limit {
__le16 seid; __le16 seid;
...@@ -1421,6 +1450,8 @@ struct i40e_aqc_configure_switching_comp_ets_data { ...@@ -1421,6 +1450,8 @@ struct i40e_aqc_configure_switching_comp_ets_data {
u8 reserved2[96]; u8 reserved2[96];
}; };
I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
u8 tc_valid_bits; u8 tc_valid_bits;
...@@ -1432,6 +1463,9 @@ struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { ...@@ -1432,6 +1463,9 @@ struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
u8 reserved1[28]; u8 reserved1[28];
}; };
I40E_CHECK_STRUCT_LEN(0x40,
i40e_aqc_configure_switching_comp_ets_bw_limit_data);
/* Configure Switching Component Bandwidth Allocation per Tc /* Configure Switching Component Bandwidth Allocation per Tc
* (indirect 0x0417) * (indirect 0x0417)
*/ */
...@@ -1443,6 +1477,8 @@ struct i40e_aqc_configure_switching_comp_bw_config_data { ...@@ -1443,6 +1477,8 @@ struct i40e_aqc_configure_switching_comp_bw_config_data {
u8 reserved1[20]; u8 reserved1[20];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
/* Query Switching Component Configuration (indirect 0x0418) */ /* Query Switching Component Configuration (indirect 0x0418) */
struct i40e_aqc_query_switching_comp_ets_config_resp { struct i40e_aqc_query_switching_comp_ets_config_resp {
u8 tc_valid_bits; u8 tc_valid_bits;
...@@ -1453,6 +1489,8 @@ struct i40e_aqc_query_switching_comp_ets_config_resp { ...@@ -1453,6 +1489,8 @@ struct i40e_aqc_query_switching_comp_ets_config_resp {
u8 reserved2[23]; u8 reserved2[23];
}; };
I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
struct i40e_aqc_query_port_ets_config_resp { struct i40e_aqc_query_port_ets_config_resp {
u8 reserved[4]; u8 reserved[4];
...@@ -1468,6 +1506,8 @@ struct i40e_aqc_query_port_ets_config_resp { ...@@ -1468,6 +1506,8 @@ struct i40e_aqc_query_port_ets_config_resp {
u8 reserved3[32]; u8 reserved3[32];
}; };
I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
/* Query Switching Component Bandwidth Allocation per Traffic Type /* Query Switching Component Bandwidth Allocation per Traffic Type
* (indirect 0x041A) * (indirect 0x041A)
*/ */
...@@ -1482,6 +1522,8 @@ struct i40e_aqc_query_switching_comp_bw_config_resp { ...@@ -1482,6 +1522,8 @@ struct i40e_aqc_query_switching_comp_bw_config_resp {
__le16 tc_bw_max[2]; __le16 tc_bw_max[2];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
/* Suspend/resume port TX traffic /* Suspend/resume port TX traffic
* (direct 0x041B and 0x041C) uses the generic SEID struct * (direct 0x041B and 0x041C) uses the generic SEID struct
*/ */
...@@ -1495,6 +1537,8 @@ struct i40e_aqc_configure_partition_bw_data { ...@@ -1495,6 +1537,8 @@ struct i40e_aqc_configure_partition_bw_data {
u8 max_bw[16]; /* bandwidth limit */ u8 max_bw[16]; /* bandwidth limit */
}; };
I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
/* Get and set the active HMC resource profile and status. /* Get and set the active HMC resource profile and status.
* (direct 0x0500) and (direct 0x0501) * (direct 0x0500) and (direct 0x0501)
*/ */
...@@ -1577,6 +1621,8 @@ struct i40e_aqc_module_desc { ...@@ -1577,6 +1621,8 @@ struct i40e_aqc_module_desc {
u8 reserved2[8]; u8 reserved2[8];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
struct i40e_aq_get_phy_abilities_resp { struct i40e_aq_get_phy_abilities_resp {
__le32 phy_type; /* bitmap using the above enum for offsets */ __le32 phy_type; /* bitmap using the above enum for offsets */
u8 link_speed; /* bitmap using the above enum bit patterns */ u8 link_speed; /* bitmap using the above enum bit patterns */
...@@ -1605,6 +1651,8 @@ struct i40e_aq_get_phy_abilities_resp { ...@@ -1605,6 +1651,8 @@ struct i40e_aq_get_phy_abilities_resp {
struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
}; };
I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
/* Set PHY Config (direct 0x0601) */ /* Set PHY Config (direct 0x0601) */
struct i40e_aq_set_phy_config { /* same bits as above in all */ struct i40e_aq_set_phy_config { /* same bits as above in all */
__le32 phy_type; __le32 phy_type;
...@@ -1788,12 +1836,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); ...@@ -1788,12 +1836,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
/* NVM Config Read (indirect 0x0704) */ /* NVM Config Read (indirect 0x0704) */
struct i40e_aqc_nvm_config_read { struct i40e_aqc_nvm_config_read {
__le16 cmd_flags; __le16 cmd_flags;
#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
#define ANVM_READ_SINGLE_FEATURE 0 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
#define ANVM_READ_MULTIPLE_FEATURES 1 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
__le16 element_count; __le16 element_count;
__le16 element_id; /* Feature/field ID */ __le16 element_id; /* Feature/field ID */
u8 reserved[2]; __le16 element_id_msw; /* MSWord of field ID */
__le32 address_high; __le32 address_high;
__le32 address_low; __le32 address_low;
}; };
...@@ -1811,21 +1859,32 @@ struct i40e_aqc_nvm_config_write { ...@@ -1811,21 +1859,32 @@ struct i40e_aqc_nvm_config_write {
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
/* Used for 0x0704 as well as for 0x0705 commands */
#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
#define I40E_AQ_ANVM_FEATURE 0
#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
struct i40e_aqc_nvm_config_data_feature { struct i40e_aqc_nvm_config_data_feature {
__le16 feature_id; __le16 feature_id;
__le16 instance_id; #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
__le16 feature_options; __le16 feature_options;
__le16 feature_selection; __le16 feature_selection;
}; };
I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
struct i40e_aqc_nvm_config_data_immediate_field { struct i40e_aqc_nvm_config_data_immediate_field {
#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 __le32 field_id;
__le16 field_id; __le32 field_value;
__le16 instance_id;
__le16 field_options; __le16 field_options;
__le16 field_value; __le16 reserved;
}; };
I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
/* Send to PF command (indirect 0x0801) id is only used by PF /* Send to PF command (indirect 0x0801) id is only used by PF
* Send to VF command (indirect 0x0802) id is only used by PF * Send to VF command (indirect 0x0802) id is only used by PF
* Send to Peer PF command (indirect 0x0803) * Send to Peer PF command (indirect 0x0803)
...@@ -2026,12 +2085,54 @@ struct i40e_aqc_get_cee_dcb_cfg_resp { ...@@ -2026,12 +2085,54 @@ struct i40e_aqc_get_cee_dcb_cfg_resp {
u8 oper_tc_bw[8]; u8 oper_tc_bw[8];
u8 oper_pfc_en; u8 oper_pfc_en;
__le16 oper_app_prio; __le16 oper_app_prio;
#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
__le32 tlv_status; __le32 tlv_status;
#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
u8 reserved[12]; u8 reserved[12];
}; };
I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
/* Set Local LLDP MIB (indirect 0x0A08)
* Used to replace the local MIB of a given LLDP agent. e.g. DCBx
*/
struct i40e_aqc_lldp_set_local_mib {
#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
u8 type;
u8 reserved0;
__le16 length;
u8 reserved1[4];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
/* Stop/Start LLDP Agent (direct 0x0A09)
* Used for stopping/starting specific LLDP agent. e.g. DCBx
*/
struct i40e_aqc_lldp_stop_start_specific_agent {
#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
u8 command;
u8 reserved[15];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
/* Add Udp Tunnel command and completion (direct 0x0B00) */ /* Add Udp Tunnel command and completion (direct 0x0B00) */
struct i40e_aqc_add_udp_tunnel { struct i40e_aqc_add_udp_tunnel {
__le16 udp_port; __le16 udp_port;
...@@ -2106,7 +2207,8 @@ struct i40e_aqc_oem_param_change { ...@@ -2106,7 +2207,8 @@ struct i40e_aqc_oem_param_change {
#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
#define I40E_AQ_OEM_PARAM_MAC 2 #define I40E_AQ_OEM_PARAM_MAC 2
__le32 param_value1; __le32 param_value1;
u8 param_value2[8]; __le16 param_value2;
u8 reserved[6];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
...@@ -2120,6 +2222,28 @@ struct i40e_aqc_oem_state_change { ...@@ -2120,6 +2222,28 @@ struct i40e_aqc_oem_state_change {
I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
/* Initialize OCSD (0xFE02, direct) */
struct i40e_aqc_opc_oem_ocsd_initialize {
u8 type_status;
u8 reserved1[3];
__le32 ocsd_memory_block_addr_high;
__le32 ocsd_memory_block_addr_low;
__le32 requested_update_interval;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
/* Initialize OCBB (0xFE03, direct) */
struct i40e_aqc_opc_oem_ocbb_initialize {
u8 type_status;
u8 reserved1[3];
__le32 ocbb_memory_block_addr_high;
__le32 ocbb_memory_block_addr_low;
u8 reserved2[4];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
/* debug commands */ /* debug commands */
/* get device id (0xFF00) uses the generic structure */ /* get device id (0xFF00) uses the generic structure */
......
...@@ -2360,6 +2360,7 @@ i40e_aq_erase_nvm_exit: ...@@ -2360,6 +2360,7 @@ i40e_aq_erase_nvm_exit:
#define I40E_DEV_FUNC_CAP_VSI 0x17 #define I40E_DEV_FUNC_CAP_VSI 0x17
#define I40E_DEV_FUNC_CAP_DCB 0x18 #define I40E_DEV_FUNC_CAP_DCB 0x18
#define I40E_DEV_FUNC_CAP_FCOE 0x21 #define I40E_DEV_FUNC_CAP_FCOE 0x21
#define I40E_DEV_FUNC_CAP_ISCSI 0x22
#define I40E_DEV_FUNC_CAP_RSS 0x40 #define I40E_DEV_FUNC_CAP_RSS 0x40
#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41