Commit 18a1a7a1 authored by Linus Torvalds's avatar Linus Torvalds

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

Pull arch/tile updates from Chris Metcalf:
 "These fix a few stray build issues seen in linux-next, and also add
  the minimal required support for perf to tilegx"

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  arch/tile: remove unused variable 'devcap'
  tile: Fix vDSO compilation issue with allyesconfig
  perf tools: Allow building for tile
  tile/perf: Support perf_events on tilegx and tilepro
  tile: Enable NMIs on return from handle_nmi() without errors
  tile: Add support for handling PMC hardware
  tile: don't use __get_cpu_var() with structure-typed arguments
  tile: avoid overflow in ns2cycles
parents 04535d27 5eb0bdf8
......@@ -3,6 +3,8 @@
config TILE
def_bool y
select HAVE_PERF_EVENTS
select USE_PMC if PERF_EVENTS
select HAVE_DMA_ATTRS
select HAVE_DMA_API_DEBUG
select HAVE_KVM if !TILEGX
......@@ -66,6 +68,10 @@ config HUGETLB_SUPER_PAGES
config GENERIC_TIME_VSYSCALL
def_bool y
# Enable PMC if PERF_EVENTS, OPROFILE, or WATCHPOINTS are enabled.
config USE_PMC
bool
# FIXME: tilegx can implement a more efficient rwsem.
config RWSEM_GENERIC_SPINLOCK
def_bool y
......
/*
* Copyright 2014 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_PERF_EVENT_H
#define _ASM_TILE_PERF_EVENT_H
#include <linux/percpu.h>
DECLARE_PER_CPU(u64, perf_irqs);
unsigned long handle_syscall_link_address(void);
#endif /* _ASM_TILE_PERF_EVENT_H */
/*
* Copyright 2014 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_PMC_H
#define _ASM_TILE_PMC_H
#include <linux/ptrace.h>
#define TILE_BASE_COUNTERS 2
/* Bitfields below are derived from SPR PERF_COUNT_CTL*/
#ifndef __tilegx__
/* PERF_COUNT_CTL on TILEPro */
#define TILE_CTL_EXCL_USER (1 << 7) /* exclude user level */
#define TILE_CTL_EXCL_KERNEL (1 << 8) /* exclude kernel level */
#define TILE_CTL_EXCL_HV (1 << 9) /* exclude hypervisor level */
#define TILE_SEL_MASK 0x7f /* 7 bits for event SEL,
COUNT_0_SEL */
#define TILE_PLM_MASK 0x780 /* 4 bits priv level msks,
COUNT_0_MASK*/
#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_PLM_MASK)
#else /* __tilegx__*/
/* PERF_COUNT_CTL on TILEGx*/
#define TILE_CTL_EXCL_USER (1 << 10) /* exclude user level */
#define TILE_CTL_EXCL_KERNEL (1 << 11) /* exclude kernel level */
#define TILE_CTL_EXCL_HV (1 << 12) /* exclude hypervisor level */
#define TILE_SEL_MASK 0x3f /* 6 bits for event SEL,
COUNT_0_SEL*/
#define TILE_BOX_MASK 0x1c0 /* 3 bits box msks,
COUNT_0_BOX */
#define TILE_PLM_MASK 0x3c00 /* 4 bits priv level msks,
COUNT_0_MASK */
#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_BOX_MASK | TILE_PLM_MASK)
#endif /* __tilegx__*/
/* Takes register and fault number. Returns error to disable the interrupt. */
typedef int (*perf_irq_t)(struct pt_regs *, int);
int userspace_perf_handler(struct pt_regs *regs, int fault);
perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq);
void release_pmc_hardware(void);
unsigned long pmc_get_overflow(void);
void pmc_ack_overflow(unsigned long status);
void unmask_pmc_interrupts(void);
void mask_pmc_interrupts(void);
#endif /* _ASM_TILE_PMC_H */
......@@ -25,6 +25,8 @@ obj-$(CONFIG_PCI) += pci_gx.o
else
obj-$(CONFIG_PCI) += pci.o
endif
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_USE_PMC) += pmc.o
obj-$(CONFIG_TILE_USB) += usb.o
obj-$(CONFIG_TILE_HVGLUE_TRACE) += hvglue_trace.o
obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o mcount_64.o
......
......@@ -313,13 +313,13 @@ intvec_\vecname:
movei r3, 0
}
.else
.ifc \c_routine, op_handle_perf_interrupt
.ifc \c_routine, handle_perf_interrupt
{
mfspr r2, PERF_COUNT_STS
movei r3, -1 /* not used, but set for consistency */
}
.else
.ifc \c_routine, op_handle_aux_perf_interrupt
.ifc \c_routine, handle_perf_interrupt
{
mfspr r2, AUX_PERF_COUNT_STS
movei r3, -1 /* not used, but set for consistency */
......@@ -946,6 +946,13 @@ STD_ENTRY(interrupt_return)
bzt r30, .Lrestore_regs
3:
/* We are relying on INT_PERF_COUNT at 33, and AUX_PERF_COUNT at 48 */
{
moveli r0, lo16(1 << (INT_PERF_COUNT - 32))
bz r31, .Lrestore_regs
}
auli r0, r0, ha16(1 << (INT_AUX_PERF_COUNT - 32))
mtspr SPR_INTERRUPT_MASK_RESET_K_1, r0
/*
* We now commit to returning from this interrupt, since we will be
......@@ -1171,6 +1178,10 @@ handle_nmi:
PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
}
FEEDBACK_REENTER(handle_nmi)
{
movei r30, 1
seq r31, r0, zero
}
j interrupt_return
STD_ENDPROC(handle_nmi)
......@@ -1835,8 +1846,9 @@ int_unalign:
/* Include .intrpt array of interrupt vectors */
.section ".intrpt", "ax"
#define op_handle_perf_interrupt bad_intr
#define op_handle_aux_perf_interrupt bad_intr
#ifndef CONFIG_USE_PMC
#define handle_perf_interrupt bad_intr
#endif
#ifndef CONFIG_HARDWALL
#define do_hardwall_trap bad_intr
......@@ -1877,7 +1889,7 @@ int_unalign:
int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
int_hand INT_PERF_COUNT, PERF_COUNT, \
op_handle_perf_interrupt, handle_nmi
handle_perf_interrupt, handle_nmi
int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
#if CONFIG_KERNEL_PL == 2
dc_dispatch INT_INTCTRL_2, INTCTRL_2
......@@ -1902,7 +1914,7 @@ int_unalign:
int_hand INT_SN_CPL, SN_CPL, bad_intr
int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
op_handle_aux_perf_interrupt, handle_nmi
handle_perf_interrupt, handle_nmi
/* Synthetic interrupt delivered only by the simulator */
int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
......@@ -509,10 +509,10 @@ intvec_\vecname:
.ifc \c_routine, do_trap
mfspr r2, GPV_REASON
.else
.ifc \c_routine, op_handle_perf_interrupt
.ifc \c_routine, handle_perf_interrupt
mfspr r2, PERF_COUNT_STS
.else
.ifc \c_routine, op_handle_aux_perf_interrupt
.ifc \c_routine, handle_perf_interrupt
mfspr r2, AUX_PERF_COUNT_STS
.endif
.endif
......@@ -971,6 +971,15 @@ STD_ENTRY(interrupt_return)
beqzt r30, .Lrestore_regs
3:
#if INT_PERF_COUNT + 1 != INT_AUX_PERF_COUNT
# error Bad interrupt assumption
#endif
{
movei r0, 3 /* two adjacent bits for the PERF_COUNT mask */
beqz r31, .Lrestore_regs
}
shli r0, r0, INT_PERF_COUNT
mtspr SPR_INTERRUPT_MASK_RESET_K, r0
/*
* We now commit to returning from this interrupt, since we will be
......@@ -1187,7 +1196,7 @@ handle_nmi:
FEEDBACK_REENTER(handle_nmi)
{
movei r30, 1
move r31, r0
cmpeq r31, r0, zero
}
j interrupt_return
STD_ENDPROC(handle_nmi)
......@@ -1491,8 +1500,9 @@ STD_ENTRY(fill_ra_stack)
.global intrpt_start
intrpt_start:
#define op_handle_perf_interrupt bad_intr
#define op_handle_aux_perf_interrupt bad_intr
#ifndef CONFIG_USE_PMC
#define handle_perf_interrupt bad_intr
#endif
#ifndef CONFIG_HARDWALL
#define do_hardwall_trap bad_intr
......@@ -1540,9 +1550,9 @@ intrpt_start:
#endif
int_hand INT_IPI_0, IPI_0, bad_intr
int_hand INT_PERF_COUNT, PERF_COUNT, \
op_handle_perf_interrupt, handle_nmi
handle_perf_interrupt, handle_nmi
int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
op_handle_perf_interrupt, handle_nmi
handle_perf_interrupt, handle_nmi
int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
#if CONFIG_KERNEL_PL == 2
dc_dispatch INT_INTCTRL_2, INTCTRL_2
......
......@@ -21,6 +21,7 @@
#include <hv/drv_pcie_rc_intf.h>
#include <arch/spr_def.h>
#include <asm/traps.h>
#include <linux/perf_event.h>
/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
#define IS_HW_CLEARED 1
......@@ -260,6 +261,23 @@ void ack_bad_irq(unsigned int irq)
pr_err("unexpected IRQ trap at vector %02x\n", irq);
}
/*
* /proc/interrupts printing:
*/
int arch_show_interrupts(struct seq_file *p, int prec)
{
#ifdef CONFIG_PERF_EVENTS
int i;
seq_printf(p, "%*s: ", prec, "PMI");
for_each_online_cpu(i)
seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
seq_puts(p, " perf_events\n");
#endif
return 0;
}
/*
* Generic, controller-independent functions:
*/
......
......@@ -68,8 +68,8 @@ void hv_message_intr(struct pt_regs *regs, int intnum)
#endif
while (1) {
rmi = hv_receive_message(__get_cpu_var(msg_state),
(HV_VirtAddr) message,
HV_MsgState *state = this_cpu_ptr(&msg_state);
rmi = hv_receive_message(*state, (HV_VirtAddr) message,
sizeof(message));
if (rmi.msglen == 0)
break;
......
......@@ -250,8 +250,6 @@ static void fixup_read_and_payload_sizes(void)
/* Scan for the smallest maximum payload size. */
for_each_pci_dev(dev) {
u32 devcap;
if (!pci_is_pcie(dev))
continue;
......
This diff is collapsed.
/*
* Copyright 2014 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/atomic.h>
#include <linux/interrupt.h>
#include <asm/processor.h>
#include <asm/pmc.h>
perf_irq_t perf_irq = NULL;
int handle_perf_interrupt(struct pt_regs *regs, int fault)
{
int retval;
if (!perf_irq)
panic("Unexpected PERF_COUNT interrupt %d\n", fault);
nmi_enter();
retval = perf_irq(regs, fault);
nmi_exit();
return retval;
}
/* Reserve PMC hardware if it is available. */
perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq)
{
return cmpxchg(&perf_irq, NULL, new_perf_irq);
}
EXPORT_SYMBOL(reserve_pmc_hardware);
/* Release PMC hardware. */
void release_pmc_hardware(void)
{
perf_irq = NULL;
}
EXPORT_SYMBOL(release_pmc_hardware);
/*
* Get current overflow status of each performance counter,
* and auxiliary performance counter.
*/
unsigned long
pmc_get_overflow(void)
{
unsigned long status;
/*
* merge base+aux into a single vector
*/
status = __insn_mfspr(SPR_PERF_COUNT_STS);
status |= __insn_mfspr(SPR_AUX_PERF_COUNT_STS) << TILE_BASE_COUNTERS;
return status;
}
/*
* Clear the status bit for the corresponding counter, if written
* with a one.
*/
void
pmc_ack_overflow(unsigned long status)
{
/*
* clear overflow status by writing ones
*/
__insn_mtspr(SPR_PERF_COUNT_STS, status);
__insn_mtspr(SPR_AUX_PERF_COUNT_STS, status >> TILE_BASE_COUNTERS);
}
/*
* The perf count interrupts are masked and unmasked explicitly,
* and only here. The normal irq_enable() does not enable them,
* and irq_disable() does not disable them. That lets these
* routines drive the perf count interrupts orthogonally.
*
* We also mask the perf count interrupts on entry to the perf count
* interrupt handler in assembly code, and by default unmask them
* again (with interrupt critical section protection) just before
* returning from the interrupt. If the perf count handler returns
* a non-zero error code, then we don't re-enable them before returning.
*
* For Pro, we rely on both interrupts being in the same word to update
* them atomically so we never have one enabled and one disabled.
*/
#if CHIP_HAS_SPLIT_INTR_MASK()
# if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32
# error Fix assumptions about which word PERF_COUNT interrupts are in
# endif
#endif
static inline unsigned long long pmc_mask(void)
{
unsigned long long mask = 1ULL << INT_PERF_COUNT;
mask |= 1ULL << INT_AUX_PERF_COUNT;
return mask;
}
void unmask_pmc_interrupts(void)
{
interrupt_mask_reset_mask(pmc_mask());
}
void mask_pmc_interrupts(void)
{
interrupt_mask_set_mask(pmc_mask());
}
......@@ -236,7 +236,15 @@ cycles_t ns2cycles(unsigned long nsecs)
* clock frequency.
*/
struct clock_event_device *dev = &__raw_get_cpu_var(tile_timer);
return ((u64)nsecs * dev->mult) >> dev->shift;
/*
* as in clocksource.h and x86's timer.h, we split the calculation
* into 2 parts to avoid unecessary overflow of the intermediate
* value. This will not lead to any loss of precision.
*/
u64 quot = (u64)nsecs >> dev->shift;
u64 rem = (u64)nsecs & ((1ULL << dev->shift) - 1);
return quot * dev->mult + ((rem * dev->mult) >> dev->shift);
}
void update_vsyscall_tz(void)
......
......@@ -104,7 +104,7 @@ $(obj-vdso32:%=%): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)
$(obj-vdso32:%=%): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32)
$(obj)/vgettimeofday32.o: $(obj)/vgettimeofday.c
$(call if_changed,cc_o_c)
$(call if_changed_rule,cc_o_c)
$(obj)/vrt_sigreturn32.o: $(obj)/vrt_sigreturn.S
$(call if_changed,as_o_S)
......
......@@ -5,7 +5,8 @@ ARCH ?= $(shell echo $(uname_M) | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
-e s/arm.*/arm/ -e s/sa110/arm/ \
-e s/s390x/s390/ -e s/parisc64/parisc/ \
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
-e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ )
-e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ \
-e s/tile.*/tile/ )
# Additional ARCH settings for x86
ifeq ($(ARCH),i386)
......
......@@ -145,6 +145,14 @@
#define CPUINFO_PROC "core ID"
#endif
#ifdef __tile__
#define mb() asm volatile ("mf" ::: "memory")
#define wmb() asm volatile ("mf" ::: "memory")
#define rmb() asm volatile ("mf" ::: "memory")
#define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory")
#define CPUINFO_PROC "model name"
#endif
#define barrier() asm volatile ("" ::: "memory")
#ifndef cpu_relax
......
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