Commit 12b0286f authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: possibly invalidate TLB before context switch


[DevSNB] If Flush TLB invalidation Mode is enabled it's the driver's
responsibility to invalidate the TLBs at least once after the previous
context switch after any GTT mappings changed (including new GTT
entries).  This can be done by a pipelined PIPE_CONTROL with TLB inv bit
set immediately before MI_SET_CONTEXT.

On GEN7 the invalidation mode is explicitly set, but this appears to be
lacking for GEN6. Since I don't know the history on this, I've decided
to dynamically read the value at ring init time, and use that value

v2: better comment (daniel)

Signed-off-by: default avatarBen Widawsky <>
parent cc0f6398
......@@ -324,6 +324,17 @@ mi_set_context(struct intel_ring_buffer *ring,
int ret;
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
ret = ring->flush(ring, 0, 0);
if (ret)
return ret;
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
......@@ -423,6 +423,13 @@ static int init_render_ring(struct intel_ring_buffer *ring)
/* This is not explicitly set for GEN6, so read the register.
* see intel_ring_mi_set_context() for why we care.
* TODO: consider explicitly setting the bit for GEN5
ring->itlb_before_ctx_switch =
if (INTEL_INFO(dev)->gen >= 6)
......@@ -116,6 +116,10 @@ struct intel_ring_buffer {
wait_queue_head_t irq_queue;
* Do an explicit TLB flush before MI_SET_CONTEXT
bool itlb_before_ctx_switch;
struct i915_hw_context *default_context;
struct drm_i915_gem_object *last_context_obj;
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