Commit 0ba3ac03 authored by Kalle Valo's avatar Kalle Valo
Browse files

Merge ath-next from ath.git

Major changes in ath10k:

* add spectral scan support for qca99x0
* add qca6164 support
parents a8b97745 ee92a209
...@@ -53,6 +53,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -53,6 +53,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.uart_pin = 7, .uart_pin = 7,
.has_shifted_cc_wraparound = true, .has_shifted_cc_wraparound = true,
.otp_exe_param = 0, .otp_exe_param = 0,
.channel_counters_freq_hz = 88000,
.fw = { .fw = {
.dir = QCA988X_HW_2_0_FW_DIR, .dir = QCA988X_HW_2_0_FW_DIR,
.fw = QCA988X_HW_2_0_FW_FILE, .fw = QCA988X_HW_2_0_FW_FILE,
...@@ -68,6 +69,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -68,6 +69,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
.uart_pin = 6, .uart_pin = 6,
.otp_exe_param = 0, .otp_exe_param = 0,
.channel_counters_freq_hz = 88000,
.fw = { .fw = {
.dir = QCA6174_HW_2_1_FW_DIR, .dir = QCA6174_HW_2_1_FW_DIR,
.fw = QCA6174_HW_2_1_FW_FILE, .fw = QCA6174_HW_2_1_FW_FILE,
...@@ -83,6 +85,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -83,6 +85,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
.uart_pin = 6, .uart_pin = 6,
.otp_exe_param = 0, .otp_exe_param = 0,
.channel_counters_freq_hz = 88000,
.fw = { .fw = {
.dir = QCA6174_HW_3_0_FW_DIR, .dir = QCA6174_HW_3_0_FW_DIR,
.fw = QCA6174_HW_3_0_FW_FILE, .fw = QCA6174_HW_3_0_FW_FILE,
...@@ -98,6 +101,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -98,6 +101,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
.uart_pin = 6, .uart_pin = 6,
.otp_exe_param = 0, .otp_exe_param = 0,
.channel_counters_freq_hz = 88000,
.fw = { .fw = {
/* uses same binaries as hw3.0 */ /* uses same binaries as hw3.0 */
.dir = QCA6174_HW_3_0_FW_DIR, .dir = QCA6174_HW_3_0_FW_DIR,
...@@ -115,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -115,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.uart_pin = 7, .uart_pin = 7,
.otp_exe_param = 0x00000700, .otp_exe_param = 0x00000700,
.continuous_frag_desc = true, .continuous_frag_desc = true,
.channel_counters_freq_hz = 150000,
.fw = { .fw = {
.dir = QCA99X0_HW_2_0_FW_DIR, .dir = QCA99X0_HW_2_0_FW_DIR,
.fw = QCA99X0_HW_2_0_FW_FILE, .fw = QCA99X0_HW_2_0_FW_FILE,
...@@ -231,6 +236,17 @@ static int ath10k_init_configure_target(struct ath10k *ar) ...@@ -231,6 +236,17 @@ static int ath10k_init_configure_target(struct ath10k *ar)
return ret; return ret;
} }
/* Some devices have a special sanity check that verifies the PCI
* Device ID is written to this host interest var. It is known to be
* required to boot QCA6164.
*/
ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
ar->dev_id);
if (ret) {
ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
return ret;
}
return 0; return 0;
} }
...@@ -1411,13 +1427,13 @@ int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) ...@@ -1411,13 +1427,13 @@ int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
void ath10k_core_stop(struct ath10k *ar) void ath10k_core_stop(struct ath10k *ar)
{ {
lockdep_assert_held(&ar->conf_mutex); lockdep_assert_held(&ar->conf_mutex);
ath10k_debug_stop(ar);
/* try to suspend target */ /* try to suspend target */
if (ar->state != ATH10K_STATE_RESTARTING && if (ar->state != ATH10K_STATE_RESTARTING &&
ar->state != ATH10K_STATE_UTF) ar->state != ATH10K_STATE_UTF)
ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
ath10k_debug_stop(ar);
ath10k_hif_stop(ar); ath10k_hif_stop(ar);
ath10k_htt_tx_free(&ar->htt); ath10k_htt_tx_free(&ar->htt);
ath10k_htt_rx_free(&ar->htt); ath10k_htt_rx_free(&ar->htt);
......
...@@ -554,6 +554,7 @@ struct ath10k { ...@@ -554,6 +554,7 @@ struct ath10k {
u8 mac_addr[ETH_ALEN]; u8 mac_addr[ETH_ALEN];
enum ath10k_hw_rev hw_rev; enum ath10k_hw_rev hw_rev;
u16 dev_id;
u32 chip_id; u32 chip_id;
u32 target_version; u32 target_version;
u8 fw_version_major; u8 fw_version_major;
...@@ -609,6 +610,8 @@ struct ath10k { ...@@ -609,6 +610,8 @@ struct ath10k {
*/ */
bool continuous_frag_desc; bool continuous_frag_desc;
u32 channel_counters_freq_hz;
struct ath10k_hw_params_fw { struct ath10k_hw_params_fw {
const char *dir; const char *dir;
const char *fw; const char *fw;
......
...@@ -323,7 +323,7 @@ void ath10k_debug_fw_stats_process(struct ath10k *ar, struct sk_buff *skb) ...@@ -323,7 +323,7 @@ void ath10k_debug_fw_stats_process(struct ath10k *ar, struct sk_buff *skb)
ret = ath10k_wmi_pull_fw_stats(ar, skb, &stats); ret = ath10k_wmi_pull_fw_stats(ar, skb, &stats);
if (ret) { if (ret) {
ath10k_warn(ar, "failed to pull fw stats: %d\n", ret); ath10k_warn(ar, "failed to pull fw stats: %d\n", ret);
goto unlock; goto free;
} }
/* Stat data may exceed htc-wmi buffer limit. In such case firmware /* Stat data may exceed htc-wmi buffer limit. In such case firmware
...@@ -386,7 +386,6 @@ free: ...@@ -386,7 +386,6 @@ free:
ath10k_debug_fw_stats_vdevs_free(&stats.vdevs); ath10k_debug_fw_stats_vdevs_free(&stats.vdevs);
ath10k_debug_fw_stats_peers_free(&stats.peers); ath10k_debug_fw_stats_peers_free(&stats.peers);
unlock:
spin_unlock_bh(&ar->data_lock); spin_unlock_bh(&ar->data_lock);
} }
......
...@@ -145,8 +145,10 @@ int ath10k_htc_send(struct ath10k_htc *htc, ...@@ -145,8 +145,10 @@ int ath10k_htc_send(struct ath10k_htc *htc,
skb_cb->eid = eid; skb_cb->eid = eid;
skb_cb->paddr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); skb_cb->paddr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
ret = dma_mapping_error(dev, skb_cb->paddr); ret = dma_mapping_error(dev, skb_cb->paddr);
if (ret) if (ret) {
ret = -EIO;
goto err_credits; goto err_credits;
}
sg_item.transfer_id = ep->eid; sg_item.transfer_id = ep->eid;
sg_item.transfer_context = skb; sg_item.transfer_context = skb;
......
...@@ -442,8 +442,10 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) ...@@ -442,8 +442,10 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
DMA_TO_DEVICE); DMA_TO_DEVICE);
res = dma_mapping_error(dev, skb_cb->paddr); res = dma_mapping_error(dev, skb_cb->paddr);
if (res) if (res) {
res = -EIO;
goto err_free_txdesc; goto err_free_txdesc;
}
skb_put(txdesc, len); skb_put(txdesc, len);
cmd = (struct htt_cmd *)txdesc->data; cmd = (struct htt_cmd *)txdesc->data;
...@@ -533,8 +535,10 @@ int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) ...@@ -533,8 +535,10 @@ int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
DMA_TO_DEVICE); DMA_TO_DEVICE);
res = dma_mapping_error(dev, skb_cb->paddr); res = dma_mapping_error(dev, skb_cb->paddr);
if (res) if (res) {
res = -EIO;
goto err_free_txbuf; goto err_free_txbuf;
}
switch (skb_cb->txmode) { switch (skb_cb->txmode) {
case ATH10K_HW_TXRX_RAW: case ATH10K_HW_TXRX_RAW:
......
...@@ -152,6 +152,6 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, ...@@ -152,6 +152,6 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
cc -= cc_prev - cc_fix; cc -= cc_prev - cc_fix;
rcc -= rcc_prev; rcc -= rcc_prev;
survey->time = CCNT_TO_MSEC(cc); survey->time = CCNT_TO_MSEC(ar, cc);
survey->time_busy = CCNT_TO_MSEC(rcc); survey->time_busy = CCNT_TO_MSEC(ar, rcc);
} }
...@@ -552,8 +552,7 @@ enum ath10k_hw_rate_cck { ...@@ -552,8 +552,7 @@ enum ath10k_hw_rate_cck {
#define SCRATCH_3_ADDRESS ar->regs->scratch_3_address #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
#define CPU_INTR_ADDRESS 0x0010 #define CPU_INTR_ADDRESS 0x0010
/* Cycle counters are running at 88MHz */ #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
#define CCNT_TO_MSEC(x) ((x) / 88000)
/* Firmware indications to the Host via SCRATCH_3 register. */ /* Firmware indications to the Host via SCRATCH_3 register. */
#define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address
......
...@@ -247,6 +247,10 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif, ...@@ -247,6 +247,10 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif,
lockdep_assert_held(&ar->conf_mutex); lockdep_assert_held(&ar->conf_mutex);
if (WARN_ON(arvif->vif->type != NL80211_IFTYPE_AP &&
arvif->vif->type != NL80211_IFTYPE_ADHOC))
return -EINVAL;
spin_lock_bh(&ar->data_lock); spin_lock_bh(&ar->data_lock);
peer = ath10k_peer_find(ar, arvif->vdev_id, addr); peer = ath10k_peer_find(ar, arvif->vdev_id, addr);
spin_unlock_bh(&ar->data_lock); spin_unlock_bh(&ar->data_lock);
...@@ -258,21 +262,34 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif, ...@@ -258,21 +262,34 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif,
if (arvif->wep_keys[i] == NULL) if (arvif->wep_keys[i] == NULL)
continue; continue;
flags = 0; switch (arvif->vif->type) {
flags |= WMI_KEY_PAIRWISE; case NL80211_IFTYPE_AP:
flags = WMI_KEY_PAIRWISE;
ret = ath10k_install_key(arvif, arvif->wep_keys[i], SET_KEY, if (arvif->def_wep_key_idx == i)
addr, flags); flags |= WMI_KEY_TX_USAGE;
if (ret < 0)
return ret;
flags = 0; ret = ath10k_install_key(arvif, arvif->wep_keys[i],
flags |= WMI_KEY_GROUP; SET_KEY, addr, flags);
if (ret < 0)
return ret;
break;
case NL80211_IFTYPE_ADHOC:
ret = ath10k_install_key(arvif, arvif->wep_keys[i],
SET_KEY, addr,
WMI_KEY_PAIRWISE);
if (ret < 0)
return ret;
ret = ath10k_install_key(arvif, arvif->wep_keys[i], SET_KEY, ret = ath10k_install_key(arvif, arvif->wep_keys[i],
addr, flags); SET_KEY, addr, WMI_KEY_GROUP);
if (ret < 0) if (ret < 0)
return ret; return ret;
break;
default:
WARN_ON(1);
return -EINVAL;
}
spin_lock_bh(&ar->data_lock); spin_lock_bh(&ar->data_lock);
peer->keys[i] = arvif->wep_keys[i]; peer->keys[i] = arvif->wep_keys[i];
...@@ -287,6 +304,9 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif, ...@@ -287,6 +304,9 @@ static int ath10k_install_peer_wep_keys(struct ath10k_vif *arvif,
* *
* FIXME: Revisit. Perhaps this can be done in a less hacky way. * FIXME: Revisit. Perhaps this can be done in a less hacky way.
*/ */
if (arvif->vif->type != NL80211_IFTYPE_ADHOC)
return 0;
if (arvif->def_wep_key_idx == -1) if (arvif->def_wep_key_idx == -1)
return 0; return 0;
...@@ -2999,6 +3019,8 @@ void ath10k_mac_tx_unlock(struct ath10k *ar, int reason) ...@@ -2999,6 +3019,8 @@ void ath10k_mac_tx_unlock(struct ath10k *ar, int reason)
IEEE80211_IFACE_ITER_RESUME_ALL, IEEE80211_IFACE_ITER_RESUME_ALL,
ath10k_mac_tx_unlock_iter, ath10k_mac_tx_unlock_iter,
ar); ar);
ieee80211_wake_queue(ar->hw, ar->hw->offchannel_tx_hw_queue);
} }
void ath10k_mac_vif_tx_lock(struct ath10k_vif *arvif, int reason) void ath10k_mac_vif_tx_lock(struct ath10k_vif *arvif, int reason)
...@@ -4122,7 +4144,8 @@ static int ath10k_add_interface(struct ieee80211_hw *hw, ...@@ -4122,7 +4144,8 @@ static int ath10k_add_interface(struct ieee80211_hw *hw,
if (ar->num_peers >= ar->max_num_peers) { if (ar->num_peers >= ar->max_num_peers) {
ath10k_warn(ar, "refusing vdev creation due to insufficient peer entry resources in firmware\n"); ath10k_warn(ar, "refusing vdev creation due to insufficient peer entry resources in firmware\n");
return -ENOBUFS; ret = -ENOBUFS;
goto err;
} }
if (ar->free_vdev_map == 0) { if (ar->free_vdev_map == 0) {
...@@ -4340,6 +4363,11 @@ static int ath10k_add_interface(struct ieee80211_hw *hw, ...@@ -4340,6 +4363,11 @@ static int ath10k_add_interface(struct ieee80211_hw *hw,
} }
} }
spin_lock_bh(&ar->htt.tx_lock);
if (!ar->tx_paused)
ieee80211_wake_queue(ar->hw, arvif->vdev_id);
spin_unlock_bh(&ar->htt.tx_lock);
mutex_unlock(&ar->conf_mutex); mutex_unlock(&ar->conf_mutex);
return 0; return 0;
......
...@@ -58,11 +58,13 @@ MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); ...@@ -58,11 +58,13 @@ MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
#define QCA988X_2_0_DEVICE_ID (0x003c) #define QCA988X_2_0_DEVICE_ID (0x003c)
#define QCA6164_2_1_DEVICE_ID (0x0041)
#define QCA6174_2_1_DEVICE_ID (0x003e) #define QCA6174_2_1_DEVICE_ID (0x003e)
#define QCA99X0_2_0_DEVICE_ID (0x0040) #define QCA99X0_2_0_DEVICE_ID (0x0040)
static const struct pci_device_id ath10k_pci_id_table[] = { static const struct pci_device_id ath10k_pci_id_table[] = {
{ PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
{ PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
{ PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
{ PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
{0} {0}
...@@ -74,11 +76,19 @@ static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { ...@@ -74,11 +76,19 @@ static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
* because of that. * because of that.
*/ */
{ QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
{ QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
}; };
...@@ -1667,8 +1677,10 @@ static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, ...@@ -1667,8 +1677,10 @@ static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
ret = dma_mapping_error(ar->dev, req_paddr); ret = dma_mapping_error(ar->dev, req_paddr);
if (ret) if (ret) {
ret = -EIO;
goto err_dma; goto err_dma;
}
if (resp && resp_len) { if (resp && resp_len) {
tresp = kzalloc(*resp_len, GFP_KERNEL); tresp = kzalloc(*resp_len, GFP_KERNEL);
...@@ -1680,8 +1692,10 @@ static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, ...@@ -1680,8 +1692,10 @@ static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
DMA_FROM_DEVICE); DMA_FROM_DEVICE);
ret = dma_mapping_error(ar->dev, resp_paddr); ret = dma_mapping_error(ar->dev, resp_paddr);
if (ret) if (ret) {
ret = EIO;
goto err_req; goto err_req;
}
xfer.wait_for_resp = true; xfer.wait_for_resp = true;
xfer.resp_len = 0; xfer.resp_len = 0;
...@@ -1810,6 +1824,7 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar) ...@@ -1810,6 +1824,7 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
case QCA988X_2_0_DEVICE_ID: case QCA988X_2_0_DEVICE_ID:
case QCA99X0_2_0_DEVICE_ID: case QCA99X0_2_0_DEVICE_ID:
return 1; return 1;
case QCA6164_2_1_DEVICE_ID:
case QCA6174_2_1_DEVICE_ID: case QCA6174_2_1_DEVICE_ID:
switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
case QCA6174_HW_1_0_CHIP_ID_REV: case QCA6174_HW_1_0_CHIP_ID_REV:
...@@ -2898,6 +2913,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, ...@@ -2898,6 +2913,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
case QCA988X_2_0_DEVICE_ID: case QCA988X_2_0_DEVICE_ID:
hw_rev = ATH10K_HW_QCA988X; hw_rev = ATH10K_HW_QCA988X;
break; break;
case QCA6164_2_1_DEVICE_ID:
case QCA6174_2_1_DEVICE_ID: case QCA6174_2_1_DEVICE_ID:
hw_rev = ATH10K_HW_QCA6174; hw_rev = ATH10K_HW_QCA6174;
break; break;
...@@ -2922,6 +2938,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev, ...@@ -2922,6 +2938,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
ar_pci->pdev = pdev; ar_pci->pdev = pdev;
ar_pci->dev = &pdev->dev; ar_pci->dev = &pdev->dev;
ar_pci->ar = ar; ar_pci->ar = ar;
ar->dev_id = pci_dev->device;
if (pdev->subsystem_vendor || pdev->subsystem_device) if (pdev->subsystem_vendor || pdev->subsystem_device)
scnprintf(ar->spec_board_id, sizeof(ar->spec_board_id), scnprintf(ar->spec_board_id, sizeof(ar->spec_board_id),
......
...@@ -57,7 +57,7 @@ static uint8_t get_max_exp(s8 max_index, u16 max_magnitude, size_t bin_len, ...@@ -57,7 +57,7 @@ static uint8_t get_max_exp(s8 max_index, u16 max_magnitude, size_t bin_len,
} }
int ath10k_spectral_process_fft(struct ath10k *ar, int ath10k_spectral_process_fft(struct ath10k *ar,
const struct wmi_phyerr *phyerr, struct wmi_phyerr_ev_arg *phyerr,
const struct phyerr_fft_report *fftr, const struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf) size_t bin_len, u64 tsf)
{ {
...@@ -73,6 +73,15 @@ int ath10k_spectral_process_fft(struct ath10k *ar, ...@@ -73,6 +73,15 @@ int ath10k_spectral_process_fft(struct ath10k *ar,
if (bin_len < 64 || bin_len > SPECTRAL_ATH10K_MAX_NUM_BINS) if (bin_len < 64 || bin_len > SPECTRAL_ATH10K_MAX_NUM_BINS)
return -EINVAL; return -EINVAL;
/* qca99x0 reports bin size as 68 bytes (64 bytes + 4 bytes) in
* report mode 2. First 64 bytes carries inband tones (-32 to +31)
* and last 4 byte carries band edge detection data (+32) mainly
* used in radar detection purpose. Strip last 4 byte to make bin
* size is valid one.
*/
if (bin_len == 68)
bin_len -= 4;
reg0 = __le32_to_cpu(fftr->reg0); reg0 = __le32_to_cpu(fftr->reg0);
reg1 = __le32_to_cpu(fftr->reg1); reg1 = __le32_to_cpu(fftr->reg1);
...@@ -118,15 +127,14 @@ int ath10k_spectral_process_fft(struct ath10k *ar, ...@@ -118,15 +127,14 @@ int ath10k_spectral_process_fft(struct ath10k *ar,
fft_sample->total_gain_db = __cpu_to_be16(total_gain_db); fft_sample->total_gain_db = __cpu_to_be16(total_gain_db);
fft_sample->base_pwr_db = __cpu_to_be16(base_pwr_db); fft_sample->base_pwr_db = __cpu_to_be16(base_pwr_db);
freq1 = __le16_to_cpu(phyerr->freq1); freq1 = phyerr->freq1;
freq2 = __le16_to_cpu(phyerr->freq2); freq2 = phyerr->freq2;
fft_sample->freq1 = __cpu_to_be16(freq1); fft_sample->freq1 = __cpu_to_be16(freq1);
fft_sample->freq2 = __cpu_to_be16(freq2); fft_sample->freq2 = __cpu_to_be16(freq2);
chain_idx = MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX); chain_idx = MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX);
fft_sample->noise = __cpu_to_be16( fft_sample->noise = __cpu_to_be16(phyerr->nf_chains[chain_idx]);
__le16_to_cpu(phyerr->nf_chains[chain_idx]));
bins = (u8 *)fftr; bins = (u8 *)fftr;
bins += sizeof(*fftr); bins += sizeof(*fftr);
......
...@@ -47,7 +47,7 @@ enum ath10k_spectral_mode { ...@@ -47,7 +47,7 @@ enum ath10k_spectral_mode {
#ifdef CONFIG_ATH10K_DEBUGFS #ifdef CONFIG_ATH10K_DEBUGFS
int ath10k_spectral_process_fft(struct ath10k *ar, int ath10k_spectral_process_fft(struct ath10k *ar,
const struct wmi_phyerr *phyerr, struct wmi_phyerr_ev_arg *phyerr,
const struct phyerr_fft_report *fftr, const struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf); size_t bin_len, u64 tsf);
int ath10k_spectral_start(struct ath10k *ar); int ath10k_spectral_start(struct ath10k *ar);
...@@ -59,7 +59,7 @@ void ath10k_spectral_destroy(struct ath10k *ar); ...@@ -59,7 +59,7 @@ void ath10k_spectral_destroy(struct ath10k *ar);
static inline int static inline int
ath10k_spectral_process_fft(struct ath10k *ar, ath10k_spectral_process_fft(struct ath10k *ar,
const struct wmi_phyerr *phyerr, struct wmi_phyerr_ev_arg *phyerr,
const struct phyerr_fft_report *fftr, const struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf) size_t bin_len, u64 tsf)
{ {
......
...@@ -37,8 +37,10 @@ struct wmi_ops { ...@@ -37,8 +37,10 @@ struct wmi_ops {
struct wmi_peer_kick_ev_arg *arg); struct wmi_peer_kick_ev_arg *arg);
int (*pull_swba)(struct ath10k *ar, struct sk_buff *skb, int (*pull_swba)(struct ath10k *ar, struct sk_buff *skb,
struct wmi_swba_ev_arg *arg); struct wmi_swba_ev_arg *arg);
int (*pull_phyerr)(struct ath10k *ar, struct sk_buff *skb, int (*pull_phyerr_hdr)(struct ath10k *ar, struct sk_buff *skb,
struct wmi_phyerr_ev_arg *arg); struct wmi_phyerr_hdr_arg *arg);
int (*pull_phyerr)(struct ath10k *ar, const void *phyerr_buf,
int left_len, struct wmi_phyerr_ev_arg *arg);
int (*pull_svc_rdy)(struct ath10k *ar, struct sk_buff *skb, int (*pull_svc_rdy)(struct ath10k *ar, struct sk_buff *skb,
struct wmi_svc_rdy_ev_arg *arg); struct wmi_svc_rdy_ev_arg *arg);
int (*pull_rdy)(struct ath10k *ar