Commit 02cf2119 authored by Ralf Baechle's avatar Ralf Baechle

Cleanup the mess in cpu_cache_init.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 942d042d
......@@ -191,7 +191,7 @@ static inline int __cpu_has_fpu(void)
return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
| MIPS_CPU_COUNTER)
static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
......@@ -200,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
case PRID_IMP_R2000:
c->cputype = CPU_R2000;
c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu())
c->options |= MIPS_CPU_FPU;
c->tlbsize = 64;
......@@ -214,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
else
c->cputype = CPU_R3000;
c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu())
c->options |= MIPS_CPU_FPU;
c->tlbsize = 64;
......@@ -297,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
#endif
case PRID_IMP_TX39:
c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB;
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
c->cputype = CPU_TX3927;
......@@ -441,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
config0 = read_c0_config();
if (((config0 & MIPS_CONF_MT) >> 7) == 1)
c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
c->options |= MIPS_CPU_TLB;
isa = (config0 & MIPS_CONF_AT) >> 13;
switch (isa) {
case 0:
......@@ -516,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
static inline void decode_configs(struct cpuinfo_mips *c)
{
/* MIPS32 or MIPS64 compliant CPU. */
c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
c->scache.flags = MIPS_CACHE_NOT_PRESENT;
......@@ -603,6 +605,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
decode_configs(c);
/*
* For historical reasons the SB1 comes with it's own variant of
* cache code which eventually will be folded into c-r4k.c. Until
* then we pretend it's got it's own cache architecture.
*/
c->options &= MIPS_CPU_4K_CACHE;
c->options |= MIPS_CPU_SB1_CACHE;
switch (c->processor_id & 0xff00) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
......
......@@ -319,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
r3k_flush_dcache_range(start, start + size);
}
void __init ld_mmu_r23000(void)
void __init r3k_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
......
......@@ -1221,7 +1221,7 @@ static inline void coherency_setup(void)
}
}
void __init ld_mmu_r4xx0(void)
void __init r4k_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
......
......@@ -496,7 +496,7 @@ static __init void probe_cache_sizes(void)
* memory management function pointers, as well as initialize
* the caches and tlbs
*/
void ld_mmu_sb1(void)
void sb1_cache_init(void)
{
extern char except_vec2_sb1;
extern char handle_vec2_sb1;
......
......@@ -410,7 +410,7 @@ static __init void tx39_probe_cache(void)
}
}
void __init ld_mmu_tx39(void)
void __init tx39_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
......
......@@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
}
}
extern void ld_mmu_r23000(void);
extern void ld_mmu_r4xx0(void);
extern void ld_mmu_tx39(void);
extern void ld_mmu_r6000(void);
extern void ld_mmu_tfp(void);
extern void ld_mmu_andes(void);
extern void ld_mmu_sb1(void);
#define __weak __attribute__((weak))
static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
void __init cpu_cache_init(void)
{
if (cpu_has_4ktlb) {
#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \
defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
ld_mmu_r4xx0();
#endif
} else switch (current_cpu_data.cputype) {
#ifdef CONFIG_CPU_R3000
case CPU_R2000:
case CPU_R3000:
case CPU_R3000A:
case CPU_R3081E:
ld_mmu_r23000();
break;
#endif
#ifdef CONFIG_CPU_TX39XX
case CPU_TX3912:
case CPU_TX3922:
case CPU_TX3927:
ld_mmu_tx39();
break;
#endif
#ifdef CONFIG_CPU_R10000
case CPU_R10000:
case CPU_R12000:
ld_mmu_r4xx0();
break;
#endif
#ifdef CONFIG_CPU_SB1
case CPU_SB1:
ld_mmu_sb1();
break;
#endif
case CPU_R8000:
panic("R8000 is unsupported");
break;
default:
panic("Yeee, unsupported cache architecture.");
if (cpu_has_3k_cache) {
extern void __weak r3k_cache_init(void);
r3k_cache_init();
return;
}
if (cpu_has_6k_cache) {
extern void __weak r6k_cache_init(void);
r6k_cache_init();
return;
}
if (cpu_has_4k_cache) {
extern void __weak r4k_cache_init(void);
r4k_cache_init();
return;
}
if (cpu_has_8k_cache) {
extern void __weak r8k_cache_init(void);
r8k_cache_init();
return;
}
if (cpu_has_tx39_cache) {
extern void __weak tx39_cache_init(void);
tx39_cache_init();
return;
}
if (cpu_has_sb1_cache) {
extern void __weak sb1_cache_init(void);
sb1_cache_init();
return;
}
panic(cache_panic);
}
......@@ -25,8 +25,19 @@
#ifndef cpu_has_4kex
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_4ktlb
#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_sb1_cache
#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
......
......@@ -217,25 +217,27 @@
* CPU Option encodings
*/
#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
/* Leave a spare bit for variant MMU types... */
#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */
#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */
#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */
#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */
#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */
#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */
#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */
#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */
#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
/*
* CPU ASE encodings
......
......@@ -13,7 +13,7 @@
*/
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
......
......@@ -17,7 +17,7 @@
#ifdef CONFIG_CPU_MIPS32_R1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
......@@ -43,7 +43,7 @@
#ifdef CONFIG_CPU_MIPS64_R1
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
......
......@@ -14,7 +14,7 @@
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
......
......@@ -16,7 +16,7 @@
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
#define cpu_has_fpu 0
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
......@@ -41,7 +41,7 @@
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4ktlb 1
#define cpu_has_4kcache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
......
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