Commit 024a6b95 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'davinci-for-linus' of...

Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci

* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (48 commits)
  Revert "rtc: omap: let device wakeup capability be configured from chip init logic"
  DM365: Added more PINMUX configurations for AEMIF
  DM365: Make CLKOUTx available
  DM365: Added PINMUX definitions for GPIO30..32
  Davinci: iotable based ioremap() interception
  Davinci: pinmux - use ioremap()
  Davinci: aintc/cpintc - use ioremap()
  Davinci: psc - use ioremap()
  Davinci: timer - use ioremap()
  Davinci: jtag_id - use ioremap()
  Davinci: da8xx: rtc - use ioremap
  Davinci: gpio - use ioremap()
  davinci: edma: fix coding style issue related to breaking lines
  davinci: edma: use BIT() wherever possible
  davinci: edma: fix coding style issue related to usage of braces
  davinci: edma: use a more intuitive name for edma_info
  Davinci: serial - conditional reset via pwremu
  Davinci: serial - use ioremap()
  Davinci: serial - remove unnecessary define
  Davinci: watchdog reset separation across socs
  ...

Fix up trivial conflict in arch/arm/Kconfig due to removal of "select
GENERIC_TIME"
parents 349e1fba 5e682ef8
......@@ -760,7 +760,6 @@ config ARCH_NOMADIK
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select ZONE_DMA
......
......@@ -7,6 +7,7 @@ config CP_INTC
bool
config ARCH_DAVINCI_DMx
select CPU_ARM926T
bool
menu "TI DaVinci Implementations"
......@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
select ARCH_HAS_CPUFREQ
config ARCH_DAVINCI_DA8XX
select CPU_ARM926T
bool
config ARCH_DAVINCI_DM365
......
......@@ -33,9 +33,6 @@
#define DA830_EVM_PHY_MASK 0x0
#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
#define DA830_EMIF25_CONTROL_BASE 0x68000000
/*
* USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
*/
......@@ -157,7 +154,7 @@ static __init void da830_evm_usb_init(void)
__func__, ret);
}
ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
if (ret) {
pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
__func__, ret);
......@@ -229,15 +226,22 @@ static const short da830_evm_mmc_sd_pins[] = {
};
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
static int da830_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA830_MMCSD_WP_PIN);
}
static int da830_evm_mmc_get_cd(int index)
{
return !gpio_get_value(DA830_MMCSD_CD_PIN);
}
static struct davinci_mmc_config da830_evm_mmc_config = {
.get_ro = da830_evm_mmc_get_ro,
.wires = 4,
.get_cd = da830_evm_mmc_get_cd,
.wires = 8,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.version = MMC_CTLR_VERSION_2,
......@@ -247,7 +251,7 @@ static inline void da830_evm_init_mmc(void)
{
int ret;
ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
if (ret) {
pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
ret);
......@@ -262,6 +266,14 @@ static inline void da830_evm_init_mmc(void)
}
gpio_direction_input(DA830_MMCSD_WP_PIN);
ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
if (ret) {
pr_warning("da830_evm_init: can not open GPIO %d\n",
DA830_MMCSD_CD_PIN);
return;
}
gpio_direction_input(DA830_MMCSD_CD_PIN);
ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
if (ret) {
pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
......@@ -360,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
static struct resource da830_evm_nand_resources[] = {
[0] = { /* First memory resource is NAND I/O window */
.start = DA830_EMIF25_ASYNC_DATA_CE3_BASE,
.end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
.start = DA8XX_AEMIF_CS3_BASE,
.end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = { /* Second memory resource is AEMIF control registers */
.start = DA830_EMIF25_CONTROL_BASE,
.end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
.start = DA8XX_AEMIF_CTL_BASE,
.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -392,7 +404,7 @@ static inline void da830_evm_init_nand(int mux_mode)
return;
}
ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
if (ret)
pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
ret);
......@@ -412,7 +424,7 @@ static inline void da830_evm_init_lcdc(int mux_mode)
{
int ret;
ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
if (ret)
pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
ret);
......@@ -492,7 +504,7 @@ static __init void da830_evm_init(void)
pr_warning("da830_evm_init: edma registration failed: %d\n",
ret);
ret = da8xx_pinmux_setup(da830_i2c0_pins);
ret = davinci_cfg_reg_list(da830_i2c0_pins);
if (ret)
pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
ret);
......@@ -508,7 +520,7 @@ static __init void da830_evm_init(void)
soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
soc_info->emac_pdata->rmii_en = 1;
ret = da8xx_pinmux_setup(da830_cpgmac_pins);
ret = davinci_cfg_reg_list(da830_cpgmac_pins);
if (ret)
pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
ret);
......@@ -527,7 +539,7 @@ static __init void da830_evm_init(void)
i2c_register_board_info(1, da830_evm_i2c_devices,
ARRAY_SIZE(da830_evm_i2c_devices));
ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
if (ret)
pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
ret);
......@@ -549,14 +561,6 @@ static int __init da830_evm_console_init(void)
console_initcall(da830_evm_console_init);
#endif
static __init void da830_evm_irq_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
soc_info->intc_irq_prios);
}
static void __init da830_evm_map_io(void)
{
da830_init();
......@@ -567,7 +571,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DA8XX_DDR_BASE + 0x100),
.map_io = da830_evm_map_io,
.init_irq = da830_evm_irq_init,
.init_irq = cp_intc_init,
.timer = &davinci_timer,
.init_machine = da830_evm_init,
MACHINE_END
......@@ -206,12 +206,12 @@ static __init void da850_evm_setup_nor_nand(void)
int ret = 0;
if (ui_card_detected & !HAS_MMC) {
ret = da8xx_pinmux_setup(da850_nand_pins);
ret = davinci_cfg_reg_list(da850_nand_pins);
if (ret)
pr_warning("da850_evm_init: nand mux setup failed: "
"%d\n", ret);
ret = da8xx_pinmux_setup(da850_nor_pins);
ret = davinci_cfg_reg_list(da850_nor_pins);
if (ret)
pr_warning("da850_evm_init: nor mux setup failed: %d\n",
ret);
......@@ -568,12 +568,12 @@ static int __init da850_evm_config_emac(void)
if (rmii_en) {
val |= BIT(8);
ret = da8xx_pinmux_setup(da850_rmii_pins);
ret = davinci_cfg_reg_list(da850_rmii_pins);
pr_info("EMAC: RMII PHY configured, MII PHY will not be"
" functional\n");
} else {
val &= ~BIT(8);
ret = da8xx_pinmux_setup(da850_cpgmac_pins);
ret = davinci_cfg_reg_list(da850_cpgmac_pins);
pr_info("EMAC: MII PHY configured, RMII PHY will not be"
" functional\n");
}
......@@ -626,7 +626,7 @@ static __init void da850_evm_init(void)
pr_warning("da850_evm_init: edma registration failed: %d\n",
ret);
ret = da8xx_pinmux_setup(da850_i2c0_pins);
ret = davinci_cfg_reg_list(da850_i2c0_pins);
if (ret)
pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
ret);
......@@ -643,7 +643,7 @@ static __init void da850_evm_init(void)
ret);
if (HAS_MMC) {
ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
if (ret)
pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
" %d\n", ret);
......@@ -679,20 +679,20 @@ static __init void da850_evm_init(void)
__raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
ret = da8xx_pinmux_setup(da850_mcasp_pins);
ret = davinci_cfg_reg_list(da850_mcasp_pins);
if (ret)
pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
ret);
da8xx_register_mcasp(0, &da850_evm_snd_data);
ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
if (ret)
pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
ret);
/* Handle board specific muxing for LCD here */
ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
if (ret)
pr_warning("da850_evm_init: evm specific lcd mux setup "
"failed: %d\n", ret);
......@@ -736,14 +736,6 @@ static int __init da850_evm_console_init(void)
console_initcall(da850_evm_console_init);
#endif
static __init void da850_evm_irq_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
soc_info->intc_irq_prios);
}
static void __init da850_evm_map_io(void)
{
da850_init();
......@@ -754,7 +746,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DA8XX_DDR_BASE + 0x100),
.map_io = da850_evm_map_io,
.init_irq = da850_evm_irq_init,
.init_irq = cp_intc_init,
.timer = &davinci_timer,
.init_machine = da850_evm_init,
MACHINE_END
......@@ -33,9 +33,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
......@@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM355_ASYNC_EMIF_CONTROL_BASE,
.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -353,17 +350,12 @@ static __init void dm355_evm_init(void)
dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
}
static __init void dm355_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm355_evm_map_io,
.init_irq = dm355_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm355_evm_init,
MACHINE_END
......@@ -30,9 +30,6 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
......@@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM355_ASYNC_EMIF_CONTROL_BASE,
.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -272,17 +269,12 @@ static __init void dm355_leopard_init(void)
ARRAY_SIZE(dm355_leopard_spi_info));
}
static __init void dm355_leopard_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm355_leopard_map_io,
.init_irq = dm355_leopard_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm355_leopard_init,
MACHINE_END
......@@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
return 0;
}
#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM365_EVM_PHY_MASK (0x2)
#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
......@@ -613,17 +608,12 @@ static __init void dm365_evm_init(void)
ARRAY_SIZE(dm365_evm_spi_info));
}
static __init void dm365_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = dm365_evm_map_io,
.init_irq = dm365_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = dm365_evm_init,
MACHINE_END
......
......@@ -41,14 +41,6 @@
#define DM644X_EVM_PHY_MASK (0x2)
#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
#define DAVINCI_CFC_ATA_BASE 0x01C66000
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
......@@ -92,8 +84,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
* limits addresses to 16M, so using addresses past 16M will wrap */
static struct resource davinci_evm_norflash_resource = {
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
......@@ -111,7 +103,7 @@ static struct platform_device davinci_evm_norflash_device = {
* It may used instead of the (default) NOR chip to boot, using TI's
* tools to install the secondary boot loader (UBL) and U-Boot.
*/
struct mtd_partition davinci_evm_nandflash_partition[] = {
static struct mtd_partition davinci_evm_nandflash_partition[] = {
/* Bootloader layout depends on whose u-boot is installed, but we
* can hide all the details.
* - block 0 for u-boot environment ... in mainline u-boot
......@@ -154,12 +146,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
static struct resource davinci_evm_nandflash_resource[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -258,32 +250,6 @@ static struct platform_device rtc_dev = {
.id = -1,
};
static struct resource ide_resources[] = {
{
.start = DAVINCI_CFC_ATA_BASE,
.end = DAVINCI_CFC_ATA_BASE + 0x7ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IDE,
.end = IRQ_IDE,
.flags = IORESOURCE_IRQ,
},
};
static u64 ide_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ide_dev = {
.name = "palm_bk3710",
.id = -1,
.resource = ide_resources,
.num_resources = ARRAY_SIZE(ide_resources),
.dev = {
.dma_mask = &ide_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct snd_platform_data dm644x_evm_snd_data;
/*----------------------------------------------------------------------*/
......@@ -704,10 +670,7 @@ static __init void davinci_evm_init(void)
pr_warning("WARNING: both IDE and Flash are "
"enabled, but they share AEMIF pins.\n"
"\tDisable IDE for NAND/NOR support.\n");
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
platform_device_register(&ide_dev);
davinci_init_ide();
} else if (HAS_NAND || HAS_NOR) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN_DISABLE);
......@@ -741,18 +704,13 @@ static __init void davinci_evm_init(void)
}
static __init void davinci_evm_irq_init(void)
{
davinci_irq_init();
}
MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
/* Maintainer: MontaVista Software <source@mvista.com> */
.phys_io = IO_PHYS,
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (DAVINCI_DDR_BASE + 0x100),
.map_io = davinci_evm_map_io,
.init_irq = davinci_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = davinci_evm_init,
MACHINE_END
......@@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
.options = 0,
};
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
static struct resource davinci_nand_resources[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -736,17 +733,12 @@ static __init void evm_init(void)
platform_device_register(&davinci_nand_device);
if (HAS_ATA)
dm646x_init_ide();
davinci_init_ide();
soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
}
static __init void davinci_dm646x_evm_irq_init(void)
{
davinci_irq_init();
}
#define DM646X_EVM_REF_FREQ 27000000
#define DM6467T_EVM_REF_FREQ 33000000
......@@ -763,7 +755,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = davinci_map_io,
.init_irq = davinci_dm646x_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = evm_init,
MACHINE_END
......@@ -773,7 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
.boot_params = (0x80000100),
.map_io = davinci_map_io,
.init_irq = davinci_dm646x_evm_irq_init,
.init_irq = davinci_irq_init,
.timer = &davinci_timer,
.init_machine = evm_init,
MACHINE_END
......
......@@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
......@@ -41,11 +42,6 @@
#define NEUROS_OSD2_PHY_MASK 0x2
#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define DAVINCI_CFC_ATA_BASE 0x01C66000
#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
......@@ -60,7 +56,7 @@
#define NAND_BLOCK_SIZE SZ_128K
struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
{
/* UBL (a few copies) plus U-Boot */
.name = "bootloader",
......@@ -98,12 +94,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
static struct resource davinci_ntosd2_nandflash_resource[] = {
{
.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
}, {
.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};