• Chris Wilson's avatar
    drm/i915: Allow concurrent read access between CPU and GPU domain · f8413190
    Chris Wilson authored
    Similar to allowing a buffer to be simultaneously read by the GPU and
    through the GTT, we wish to allow readback of the pages through the CPU
    domain whilst they are also being read by the GPU. Domain coherency
    is managed by allowing multiple readers, but only a single writer.
    This is used by mesa for its program cache which it may search for every
    new program every frame and then renews should it need to add. During
    renewal, mesa copies the program bo currently executing through a CPU
    mapping onto the new bo. This patch allows the search and that copy to
    proceed without causing a stall on the current batch.
    Testcase: i-g-t/tests/gem_cpu_concurrent_blit
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>