• Chris Wilson's avatar
    drm/i915: Export ability of changing cache levels to userspace · e6994aee
    Chris Wilson authored
    By selecting the cache level (essentially whether or not the CPU snoops
    any updates to the bo, and on more recent machines whether it resides
    inside the CPU's last-level-cache) a userspace driver is able to then
    manage all of its memory within buffer objects, if it so desires. This
    enables the userspace driver to accelerate uploads and more importantly
    downloads from the GPU and to able to mix CPU and GPU rendering/activity
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    [danvet: Added code comment about where we plan to stuff platform
    specific cacheing control bits in the ioctl struct.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
i915_gem.c 106 KB