• Kimball Murray's avatar
    [PATCH] x86_64: avoid IRQ0 ioapic pin collision · e0c1e9bf
    Kimball Murray authored
    
    
    The patch addresses a problem with ACPI SCI interrupt entry, which gets
    re-used, and the IRQ is assigned to another unrelated device.  The patch
    corrects the code such that SCI IRQ is skipped and duplicate entry is
    avoided.  Second issue came up with VIA chipset, the problem was caused by
    original patch assigning IRQs starting 16 and up.  The VIA chipset uses
    4-bit IRQ register for internal interrupt routing, and therefore cannot
    handle IRQ numbers assigned to its devices.  The patch corrects this
    problem by allowing PCI IRQs below 16.
    
    Cc: len.brown@intel.com
    
    Signed-off by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
    Signed-off-by: default avatarAndi Kleen <ak@suse.de>
    Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
    e0c1e9bf
io_apic.c 53.8 KB