• Bruce Allan's avatar
    e1000e: add support for LTR on I217/I218 · cf8fb73c
    Bruce Allan authored
    
    
    Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
    GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
    when link is up (which must not exceed the maximum latency supported
    by the platform), otherwise specify there is no LTR requirement.
    Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
    latencies in the LTR Extended Capability Structure in the PCIe Extended
    Capability register set, on this device LTR is set by writing the
    equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
    set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
    message to the PMC.
    Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
    Tested-by: default avatarJeff Pieper <jeffrey.e.pieper@intel.com>
    Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
    cf8fb73c
ich8lan.c 129 KB