• Jungseok Lee's avatar
    arm64: mm: Implement 4 levels of translation tables · c79b954b
    Jungseok Lee authored
    
    
    This patch implements 4 levels of translation tables since 3 levels
    of page tables with 4KB pages cannot support 40-bit physical address
    space described in [1] due to the following issue.
    
    It is a restriction that kernel logical memory map with 4KB + 3 levels
    (0xffffffc000000000-0xffffffffffffffff) cannot cover RAM region from
    544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create
    mapping for this region in map_mem function since __phys_to_virt for
    this region reaches to address overflow.
    
    If SoC design follows the document, [1], over 32GB RAM would be placed
    from 544GB. Even 64GB system is supposed to use the region from 544GB
    to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels
    of page tables to avoid hacking __virt_to_phys and __phys_to_virt.
    
    However, it is recommended 4 levels of page table should be only enabled
    if memory map is too sparse or there is about 512GB RAM.
    
    References
    ----------
    [1]: Principles of ARM Memory Maps, White Paper, Issue C
    Signed-off-by: default avatarJungseok Lee <jays.lee@samsung.com>
    Reviewed-by: default avatarSungjinn Chung <sungjinn.chung@samsung.com>
    Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
    Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
    Reviewed-by: default avatarSteve Capper <steve.capper@linaro.org>
    [catalin.marinas@arm.com: MEMBLOCK_INITIAL_LIMIT removed, same as PUD_SIZE]
    [catalin.marinas@arm.com: early_ioremap_init() updated for 4 levels]
    [catalin.marinas@arm.com: 48-bit VA depends on BROKEN until KVM is fixed]
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Tested-by: default avatarJungseok Lee <jungseoklee85@gmail.com>
    c79b954b