Charles Jacobsen authored Jul 11, 2014 and Vikram Narayanan committed Oct 25, 2016

In the process of debugging, major corrections and
debug checks implemented (this is a big squash):
-- coded up entry checks documented in Intel SDM
   V3 chp 26 (this should help later if settings
   are changed, make it less risky to experiment
   and give more confidence)
-- fixed host tr base addr bug (the worst bug! caused
   system to hang and then crash, since the tss
   was erroneous...)
-- fixed vmx_entry to properly set host rsp before
   entry
-- setting host sysenter and idt info
-- fixed cs ar bytes bug
-- fixed gdt limit bug
-- fixed tr type bug
-- extra settings added to cr0 and cr4, but may
   not be needed ... (debug fix attempt)
-- lstar mstar autoload, may not be needed ...
   (debug fix attempt)