• Jacob Pan's avatar
    x86/mrst: Fix boot crash caused by incorrect pin to irq mapping · 9d90e49d
    Jacob Pan authored
    Moorestown systems crash on boot because the secondary CPU
    clockevent (apbt1) will fail to request irq#1, which does not
    have ioapic chip in its irq_desc[] entry.
    Moorestown platform does not have ISA bus nor legacy IRQs. It
    reuses the range of legacy IRQs for regular device interrupts.
    The routing information of early system device IRQs (timers) are
    obtained from firmware provided SFI tables. We reuse/fake MP
    configuration table to facilitate IRQ setup with IOAPIC.
    Maintaining a 1:1 mapping of IOAPIC pin (RTE entry) and IRQ#
    makes routing information clean and easy to understand on
    Moorestown. Though optional.
    This patch allows SFI timer and vRTC IRQ to be treated as ISA
    IRQ so that pin2irq mapping will be 1:1.
    Also fixed MP table type and use macros to clearly set MP IRQ
    entries. As a result, apbt timer and RTC interrupts on
    Moorestown are within legacy IRQ range:
     # cat /proc/interrupts
                CPU0       CPU1
       0:      11249          0   IO-APIC-edge      apbt0
       1:          0      12271   IO-APIC-edge      apbt1
       8:        887          0   IO-APIC-fasteoi   dw_spi
      13:          0          0   IO-APIC-fasteoi   INTEL_MID_DMAC2
      14:          0          0   IO-APIC-fasteoi   rtc0
    Further discussion of this patch can be found at:
      https://lkml.org/lkml/2010/6/10/70Suggested-by: default avatar"Eric W. Biederman" <ebiederm@xmission.com>
    Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
    Cc: Feng Tang <feng.tang@intel.com>
    Cc: Alan Cox <alan@linux.intel.com>
    Cc: Arjan van de Ven <arjan@linux.intel.com>
    Link: http://lkml.kernel.org/r/1302286980-21139-1-git-send-email-jacob.jun.pan@linux.intel.comSigned-off-by: default avatarIngo Molnar <mingo@elte.hu>
mrst.c 21.2 KB