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  • Lennert Buytenhek's avatar
    [ARM] Feroceon: L2 cache support · 99c6dc11
    Lennert Buytenhek authored
    
    
    This patch adds support for the unified Feroceon L2 cache controller
    as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
    families of ARM SoCs.
    
    Note that:
    
    - Page table walks are outer uncacheable on Kirkwood and Discovery
      Duo, since the ARMv5 spec provides no way to indicate outer
      cacheability of page table walks (specifying it in TTBR[4:3] is
      an ARMv6+ feature).
    
      This requires adding L2 cache clean instructions to
      proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
      tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
      by defining a new TLB type (TLB_FEROCEON) which is almost identical
      to the v4wbi one but provides a TLB_L2CLEAN_FR flag.
    
    - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
      range by MVA' and 'invalidate L2 range by MVA') operations, and this
      patch uses those range operations for all Linux outer cache
      operations, as they are faster than the regular per-line operations.
    
      L2 range operations are not interruptible on this hardware, which
      avoids potential livelock issues, but can be bad for interrupt
      latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
      allows you to select the maximum range size to operate on at once.
      (Valid range is between one cache line and one 4KiB page, and must
      be a multiple of the line size.)
    
    Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
    99c6dc11