• Russell King's avatar
    [ARM] Set bit 4 on section mappings correctly depending on CPU · 8799ee9f
    Russell King authored
    On some CPUs, bit 4 of section mappings means "update the
    cache when written to".  On others, this bit is required to
    be one, and others it's required to be zero.  Finally, on
    ARMv6 and above, setting it turns on "no execute" and prevents
    speculative prefetches.
    With all these combinations, no one value fits all CPUs, so we
    have to pick a value depending on the CPU type, and the area
    we're mapping.
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
proc-arm1020.S 13.1 KB