• Tony Luck's avatar
    [IA64] Change default PSR.ac from '1' to '0' (Fix erratum #237) · c0b5a64d
    Tony Luck authored
    April 2014 Itanium processor specification update:
    describes this erratum:
    237. Under a complex set of conditions, store to load forwarding for a
    sub 8-byte load may complete incorrectly
    Problem: A load instruction may complete incorrectly when a code sequence
    using 4-byte or smaller load and store operations to the same address
    is executed in combination with specific timing of all the following
    concurrent conditions: store to load forwarding, alignment checking
    enabled, a mis-predicted branch, and complex cache utilization activity.
    Implication: The affected sub 8-byte instruction may complete
    incorrectly resulting in unpredictable system behavior. There is an
    extremely low probability of exposure due to the significant number of
    complex microarchitectural concurrent conditions required to encounter
    the erratum.
    Workaround: Set PSR.ac = 0 to completely avoid the erratum. Disabling
    Hyper-Threading will significantly reduce exposure to the conditions
    that contribute to encountering the erratum.
    Status: See the Summary Table of Changes for the affected steppings.
    [Table of changes essentially lists all models from McKinley to Tukwila]
    The PSR.ac bit controls whether the processor will always generate
    an unaligned reference trap (0x5a00) for a misaligned data access
    (when PSR.ac=1) or if it will let the access succeed when running
    on a cpu that implements logic to handle some unaligned accesses.
    Way back in 2008 in commit b704882e
      [IA64] Rationalize kernel mode alignment checking
    we made the decision to always enable strict checking. We were
    already doing so in trap/interrupt context because the common
    preamble code set this bit - but the rest of supervisor code
    (and by inheritance user code) ran with PSR.ac=0.
    We now reverse that decision and set PSR.ac=0 everywhere in the
    kernel (also inherited by user processes). This will avoid the
    erratum using the method described in the Itanium specification
    update.  Net effect for users is that the processor will handle
    unaligned access when it can (typically with a tiny performance
    bubble in the pipeline ... but much less invasive than taking a
    trap and having the OS perform the access).
    Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
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