• Ben Cahill's avatar
    iwlagn: Use iwl_write8() for CSR_INT_COALESCING register · 74ba67ed
    Ben Cahill authored
    
    
    CSR_INT_COALESCING previously had only one, but now has two single-byte fields.
    With only one single-byte field (lowest order byte) it was okay to write via
    iwl_write32(), but now with two, an iwl_write32() to the lower order field
    clobbers the other field (odd-address CSR_INT_PERIODIC_REG, offset 0x5), and an
    iwl_write32() to CSR_INT_PERIODIC_REG could clobber the lowest byte of the
    next-higher register (CSR_INT, offset 0x8).
    
    Fortunately, no bad side effects have been produced by the iwl_write32()
    usage, due to order of execution (low order byte was always written before
    higher order byte), and the fact that writing "0" to the low byte of the
    next higher register has no effect (only action is when writing "1"s).
    
    Nonetheless, this cleans up the accesses so no bad side effects might occur
    in the future, if execution order changes, or more bit fields get added to
    CSR_INT_COALESCING.
    
    Add some comments regarding periodic interrupt usage.
    Signed-off-by: default avatarBen Cahill <ben.m.cahill@intel.com>
    Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
    Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
    74ba67ed
iwl-core.c 91.5 KB