• Nicolas Pitre's avatar
    [ARM] fixmap support · 5f0fbf9e
    Nicolas Pitre authored
    This is the minimum fixmap interface expected to be implemented by
    architectures supporting highmem.
    We have a second level page table already allocated and covering
    0xfff00000-0xffffffff because the exception vector page is located
    at 0xffff0000, and various cache tricks already use some entries above
    0xffff0000.  Therefore the PTEs covering 0xfff00000-0xfffeffff are free
    to be used.
    However the XScale cache flushing code already uses virtual addresses
    between 0xfffe0000 and 0xfffeffff.
    So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.
    The Documentation/arm/memory.txt information is updated accordingly,
    including the information about the actual top of DMA memory mapping
    region which didn't match the code.
    Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
memory.txt 2.89 KB