Update the sh7372 clock code to set the RT side
set of MSTP bits to a fixed disabled state.

The sh7372 SoC contains two sets of MSTP bits,
one for the ARM (SYS) side, and one for the
SH4AL-DSP (RT) side. The actual clock associated
with the MSTP bit will only be stopped when both
sides have set the MSTP bit to disabled mode.

Some MSTP bits are enabled by default after
hardware reset, so this patch adjusts the code
to disable all MSTP bits associated with the RT
side to allow the SYS side to have full control.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>