• Paul Walmsley's avatar
    OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behind Kconfig · 18862cbe
    Paul Walmsley authored
    The code that reprograms the SDRC memory controller during CORE DVFS,
    mach-omap2/sram34xx.S:omap3_sram_configure_core_dpll(), does not
    ensure that all L3 initiators are prevented from accessing the SDRAM
    before modifying the SDRC AC timing and MR registers.  This can cause
    memory to be corrupted or cause the SDRC to enter an unpredictable
    state.  This patch places that code behind a Kconfig option,
    CONFIG_OMAP3_SDRC_AC_TIMING for now, and adds a note explaining what
    is going on.  Ideally the code can be added back in once supporting
    code is present to ensure that other initiators aren't touching the
    SDRAM.  At the very least, these registers should be reprogrammable
    during kernel init to deal with buggy bootloaders.  Users who know
    that all other system initiators will not be touching the SDRAM can
    also re-enable this Kconfig option.
    
    This is a modification of a patch originally written by Rajendra Nayak
    <rnayak@ti.com> (the original is at http://patchwork.kernel.org/patch/51927/
    
    ).
    Rather than removing the code completely, this patch just comments it out.
    
    Thanks to Benoît Cousson <b-cousson@ti.com> and Christophe Sucur
    <c-sucur@ti.com> for explaining the technical basis for this and for
    explaining what can be done to make this path work in future code.
    Thanks to Richard Woodruff <r-woodruff2@ti.com>, Nishanth Menon
    <nm@ti.com>, and Olof Johansson <olof@lixom.net> for their comments.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Cc: Rajendra Nayak <rnayak@ti.com>
    Cc: Christophe Sucur <c-sucur@ti.com>
    Cc: Benoît Cousson <b-cousson@ti.com>
    Cc: Richard Woodruff <r-woodruff2@ti.com>
    Cc: Nishanth Menon <nm@ti.com>
    Cc: Olof Johansson <olof@lixom.net>
    18862cbe
sram34xx.S 9.57 KB