proc-v7.S 10 KB
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/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
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#include <linux/init.h>
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#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

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#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
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#include "proc-v7-2level.S"
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#endif
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ENTRY(cpu_v7_proc_init)
	mov	pc, lr
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ENDPROC(cpu_v7_proc_init)
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ENTRY(cpu_v7_proc_fin)
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	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
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	mov	pc, lr
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ENDPROC(cpu_v7_proc_fin)
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/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
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 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
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 */
	.align	5
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	.pushsection	.idmap.text, "ax"
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ENTRY(cpu_v7_reset)
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	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
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 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
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	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
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	mov	pc, r0
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ENDPROC(cpu_v7_reset)
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	.popsection
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/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
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	dsb					@ WFI may enter a low-power mode
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	wfi
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	mov	pc, lr
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ENDPROC(cpu_v7_do_idle)
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ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
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ENDPROC(cpu_v7_dcache_clean_area)
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	string	cpu_v7_name, "ARMv7 Processor"
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	.align

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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
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.equ	cpu_v7_suspend_size, 4 * 8
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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	stmfd	sp!, {r4 - r10, lr}
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	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
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	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
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	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
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	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
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	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
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	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
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	stmia	r0, {r6 - r11}
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	ldmfd	sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
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	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
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	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
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	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
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	ldmia	r0, {r6 - r11}
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	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
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#ifndef CONFIG_ARM_LPAE
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	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
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#endif
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	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
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	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
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	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
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	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
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	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
	isb
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	dsb
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	mov	r0, r8			@ control register
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	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

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	__CPUINIT
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/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
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__v7_ca5mp_setup:
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__v7_ca9mp_setup:
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	mov	r10, #(1 << 0)			@ TLB ops broadcasting
	b	1f
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__v7_ca7mp_setup:
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__v7_ca15mp_setup:
	mov	r10, #0
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#ifdef CONFIG_SMP
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	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
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	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
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	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
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#endif
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__v7_setup:
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	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}
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	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
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	bne	3f
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	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
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	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number
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	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
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#ifdef CONFIG_ARM_ERRATA_430973
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	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
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#endif
#ifdef CONFIG_ARM_ERRATA_458693
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	teq	r6, #0x20			@ only present in r2p0
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	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
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#endif
#ifdef CONFIG_ARM_ERRATA_460075
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	teq	r6, #0x20			@ only present in r2p0
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	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
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#endif
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	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
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#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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	teq	r5, #0x00200000			@ only present in r2p*
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	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
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#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
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	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
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1:
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#endif
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3:	mov	r10, #0
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	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
	dsb
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#ifdef CONFIG_MMU
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	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
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	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
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	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
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	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
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#endif
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	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
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#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
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#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
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#endif
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   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
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 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
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	mov	pc, lr				@ return to head.S:__ret
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ENDPROC(__v7_setup)
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	.align	2
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__v7_setup_stack:
	.space	4 * 11				@ 11 registers

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	__INITDATA

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	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
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	.section ".rodata"

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	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
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	.align

	.section ".proc.info.init", #alloc, #execinstr

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	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
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			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
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	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
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			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
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	W(b)	\initfunc
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	.long	cpu_arch_name
	.long	cpu_elf_name
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	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
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	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
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.endm

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#ifndef CONFIG_ARM_LPAE
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	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

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	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
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	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
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#endif	/* CONFIG_ARM_LPAE */
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	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

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	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

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	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
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	__v7_proc __v7_setup
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	.size	__v7_proc_info, . - __v7_proc_info