intel_hdmi.c 21.4 KB
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/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
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#include "drm_edid.h"
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#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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	return container_of(encoder, struct intel_hdmi, base.base);
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}

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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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{
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	uint8_t *data = (uint8_t *)frame;
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	uint8_t sum = 0;
	unsigned i;

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	frame->checksum = 0;
	frame->ecc = 0;
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	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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		sum += data[i];

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	frame->checksum = 0x100 - sum;
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}

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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
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{
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	switch (frame->type) {
	case DIP_TYPE_AVI:
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		return VIDEO_DIP_SELECT_AVI;
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	case DIP_TYPE_SPD:
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		return VIDEO_DIP_SELECT_SPD;
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	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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		return 0;
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	}
}

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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
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{
	switch (frame->type) {
	case DIP_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI;
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	case DIP_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD;
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	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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		return 0;
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	}
}

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static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
	case DIP_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD_HSW;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}

static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(pipe);
	case DIP_TYPE_SPD:
		return HSW_TVIDEO_DIP_SPD_DATA(pipe);
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}

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static void g4x_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
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{
	uint32_t *data = (uint32_t *)frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	u32 val = I915_READ(VIDEO_DIP_CTL);
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	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	val &= ~VIDEO_DIP_PORT_MASK;
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	if (intel_hdmi->sdvox_reg == SDVOB)
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		val |= VIDEO_DIP_PORT_B;
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	else if (intel_hdmi->sdvox_reg == SDVOC)
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		val |= VIDEO_DIP_PORT_C;
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	else
		return;

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	val |= VIDEO_DIP_ENABLE;
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}

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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(VIDEO_DIP_CTL, val);
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}

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static void ibx_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(reg);

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	val &= ~VIDEO_DIP_PORT_MASK;
	switch (intel_hdmi->sdvox_reg) {
	case HDMIB:
		val |= VIDEO_DIP_PORT_B;
		break;
	case HDMIC:
		val |= VIDEO_DIP_PORT_C;
		break;
	case HDMID:
		val |= VIDEO_DIP_PORT_D;
		break;
	default:
		return;
	}

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	intel_wait_for_vblank(dev, intel_crtc->pipe);

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	val |= VIDEO_DIP_ENABLE;

	I915_WRITE(reg, val);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
}

static void cpt_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
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{
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	uint32_t *data = (uint32_t *)frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	u32 val = I915_READ(reg);
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	intel_wait_for_vblank(dev, intel_crtc->pipe);

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
	if (frame->type == DIP_TYPE_AVI)
		val |= VIDEO_DIP_ENABLE_AVI;
	else
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		val &= ~g4x_infoframe_enable(frame);
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	val |= VIDEO_DIP_ENABLE;

	I915_WRITE(reg, val);
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	u32 val = I915_READ(reg);
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	intel_wait_for_vblank(dev, intel_crtc->pipe);

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	val |= VIDEO_DIP_ENABLE;
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	I915_WRITE(reg, val);
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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}

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static void hsw_write_infoframe(struct drm_encoder *encoder,
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				struct dip_infoframe *frame)
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{
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	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(ctl_reg);
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	if (data_reg == 0)
		return;

	intel_wait_for_vblank(dev, intel_crtc->pipe);

	val &= ~hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
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	val |= hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);
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}

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static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	if (!intel_hdmi->has_hdmi_sink)
		return;

	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}

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void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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					 struct drm_display_mode *adjusted_mode)
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{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};

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	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;

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	intel_set_infoframe(encoder, &avi_if);
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}

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void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
	struct dip_infoframe spd_if;

	memset(&spd_if, 0, sizeof(spd_if));
	spd_if.type = DIP_TYPE_SPD;
	spd_if.ver = DIP_VERSION_SPD;
	spd_if.len = DIP_LEN_SPD;
	strcpy(spd_if.body.spd.vn, "Intel");
	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	spd_if.body.spd.sdi = DIP_SPD_PC;

	intel_set_infoframe(encoder, &spd_if);
}

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static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	u32 sdvox;

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	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
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	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
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	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
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	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;

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	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

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	if (intel_hdmi->has_audio) {
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		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
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		sdvox |= SDVO_AUDIO_ENABLE;
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		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
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		intel_write_eld(encoder, adjusted_mode);
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	}
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	if (HAS_PCH_CPT(dev))
		sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
	else if (intel_crtc->pipe == 1)
		sdvox |= SDVO_PIPE_B_SELECT;
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	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
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	intel_hdmi_set_spd_infoframe(encoder);
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}

static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	u32 temp;
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	u32 enable_bits = SDVO_ENABLE;

	if (intel_hdmi->has_audio)
		enable_bits |= SDVO_AUDIO_ENABLE;
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	temp = I915_READ(intel_hdmi->sdvox_reg);
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	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
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	if (HAS_PCH_SPLIT(dev)) {
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		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
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	}

	if (mode != DRM_MODE_DPMS_ON) {
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		temp &= ~enable_bits;
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	} else {
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		temp |= enable_bits;
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	}
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	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);
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	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
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	if (HAS_PCH_SPLIT(dev)) {
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		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
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	}
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}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
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		return MODE_CLOCK_LOW;
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	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

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static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit;

	switch (intel_hdmi->sdvox_reg) {
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	case SDVOB:
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		bit = HDMIB_HOTPLUG_LIVE_STATUS;
		break;
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	case SDVOC:
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		bit = HDMIC_HOTPLUG_LIVE_STATUS;
		break;
	default:
		bit = 0;
		break;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

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static enum drm_connector_status
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intel_hdmi_detect(struct drm_connector *connector, bool force)
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{
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	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
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	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
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	enum drm_connector_status status = connector_status_disconnected;
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	if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
		return status;

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	intel_hdmi->has_hdmi_sink = false;
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	intel_hdmi->has_audio = false;
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	edid = drm_get_edid(connector,
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			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
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	if (edid) {
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		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
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			status = connector_status_connected;
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			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
				intel_hdmi->has_hdmi_sink =
						drm_detect_hdmi_monitor(edid);
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			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
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		}
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		connector->display_info.raw_edid = NULL;
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		kfree(edid);
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	}
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	if (status == connector_status_connected) {
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		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				(intel_hdmi->force_audio == HDMI_AUDIO_ON);
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	}

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	return status;
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}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
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	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
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	struct drm_i915_private *dev_priv = connector->dev->dev_private;
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	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

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	return intel_ddc_get_modes(connector,
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				   intel_gmbus_get_adapter(dev_priv,
							   intel_hdmi->ddc_bus));
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}

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static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
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			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
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	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

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static int
intel_hdmi_set_property(struct drm_connector *connector,
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			struct drm_property *property,
			uint64_t val)
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{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
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	struct drm_i915_private *dev_priv = connector->dev->dev_private;
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	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

563
	if (property == dev_priv->force_audio_property) {
564
		enum hdmi_force_audio i = val;
565
566
567
		bool has_audio;

		if (i == intel_hdmi->force_audio)
568
569
			return 0;

570
		intel_hdmi->force_audio = i;
571

572
		if (i == HDMI_AUDIO_AUTO)
573
574
			has_audio = intel_hdmi_detect_audio(connector);
		else
575
			has_audio = (i == HDMI_AUDIO_ON);
576

577
578
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
579

580
		intel_hdmi->has_audio = has_audio;
581
582
583
		goto done;
	}

584
585
586
587
588
589
590
591
	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

592
593
594
595
596
597
598
599
600
601
602
603
604
	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

605
606
607
608
static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
609
	kfree(connector);
610
611
}

612
613
614
615
616
617
618
619
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
	.dpms = intel_ddi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_ddi_mode_set,
	.commit = intel_encoder_commit,
};

620
621
622
623
624
625
626
627
628
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.dpms = intel_hdmi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_hdmi_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
629
	.dpms = drm_helper_connector_dpms,
630
631
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
632
	.set_property = intel_hdmi_set_property,
633
634
635
636
637
638
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
639
	.best_encoder = intel_best_encoder,
640
641
642
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
643
	.destroy = intel_encoder_destroy,
644
645
};

646
647
648
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
649
	intel_attach_force_audio_property(connector);
650
	intel_attach_broadcast_rgb_property(connector);
651
652
}

653
654
655
656
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
657
	struct intel_encoder *intel_encoder;
658
	struct intel_connector *intel_connector;
659
	struct intel_hdmi *intel_hdmi;
660
	int i;
661

662
663
	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
664
		return;
665
666
667

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
668
		kfree(intel_hdmi);
669
670
671
		return;
	}

672
	intel_encoder = &intel_hdmi->base;
673
674
675
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

676
	connector = &intel_connector->base;
677
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
678
			   DRM_MODE_CONNECTOR_HDMIA);
679
680
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

681
	intel_encoder->type = INTEL_OUTPUT_HDMI;
682

683
	connector->polled = DRM_CONNECTOR_POLL_HPD;
684
	connector->interlace_allowed = 1;
685
	connector->doublescan_allowed = 0;
686
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
687
688

	/* Set up the DDC bus. */
689
	if (sdvox_reg == SDVOB) {
690
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
691
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
692
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
693
	} else if (sdvox_reg == SDVOC) {
694
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
695
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
696
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
697
	} else if (sdvox_reg == HDMIB) {
698
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
699
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
700
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
701
	} else if (sdvox_reg == HDMIC) {
702
		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
703
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
704
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
705
	} else if (sdvox_reg == HDMID) {
706
		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
707
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
708
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
	} else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
		DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		intel_hdmi->ddi_port = PORT_B;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
		DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		intel_hdmi->ddi_port = PORT_C;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
		DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		intel_hdmi->ddi_port = PORT_D;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
727
728
729
730
	} else {
		/* If we got an unknown sdvox_reg, things are pretty much broken
		 * in a way that we should let the kernel know about it */
		BUG();
731
	}
732

733
	intel_hdmi->sdvox_reg = sdvox_reg;
734

735
	if (!HAS_PCH_SPLIT(dev)) {
736
		intel_hdmi->write_infoframe = g4x_write_infoframe;
737
		I915_WRITE(VIDEO_DIP_CTL, 0);
738
739
740
741
	} else if (IS_VALLEYVIEW(dev)) {
		intel_hdmi->write_infoframe = vlv_write_infoframe;
		for_each_pipe(i)
			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
742
743
744
745
746
747
748
	} else if (IS_HASWELL(dev)) {
		/* FIXME: Haswell has a new set of DIP frame registers, but we are
		 * just doing the minimal required for HDMI to work at this stage.
		 */
		intel_hdmi->write_infoframe = hsw_write_infoframe;
		for_each_pipe(i)
			I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
749
750
751
752
753
754
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
		for_each_pipe(i)
			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
755
756
757
		for_each_pipe(i)
			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
	}
758

759
760
761
762
	if (IS_HASWELL(dev))
		drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
	else
		drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
763

764
765
	intel_hdmi_add_properties(intel_hdmi, connector);

766
	intel_connector_attach_encoder(intel_connector, intel_encoder);
767
768
769
770
771
772
773
774
775
776
777
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}