i7core_edac.c 59.7 KB
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/* Intel i7 core/Nehalem Memory Controller kernel module
 *
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 * This driver supports the memory controllers found on the Intel
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 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
 * and Westmere-EP.
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 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
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 * Copyright (c) 2009-2010 by:
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 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/edac.h>
#include <linux/mmzone.h>
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#include <linux/edac_mce.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include "edac_core.h"

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/* Static vars */
static LIST_HEAD(i7core_edac_list);
static DEFINE_MUTEX(i7core_edac_lock);
static int probed;

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static int use_pci_fixup;
module_param(use_pci_fixup, int, 0444);
MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
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/*
 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
 * registers start at bus 255, and are not reported by BIOS.
 * We currently find devices with only 2 sockets. In order to support more QPI
 * Quick Path Interconnect, just increment this number.
 */
#define MAX_SOCKET_BUSES	2


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/*
 * Alter this version for the module when modifications are made
 */
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#define I7CORE_REVISION    " Ver: 1.0.0"
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#define EDAC_MOD_STR      "i7core_edac"

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

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	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90
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  #define MC_CFG_UNLOCK		0x02
  #define MC_CFG_LOCK		0x00
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	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

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/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

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/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
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#define MC_SSRCONTROL		0x48
  #define SSR_MODE_DISABLE	0x00
  #define SSR_MODE_ENABLE	0x01
  #define SSR_MODE_MASK		0x03

#define MC_SCRUB_CONTROL	0x4c
  #define STARTSCRUB		(1 << 24)

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#define MC_COR_ECC_CNT_0	0x80
#define MC_COR_ECC_CNT_1	0x84
#define MC_COR_ECC_CNT_2	0x88
#define MC_COR_ECC_CNT_3	0x8c
#define MC_COR_ECC_CNT_4	0x90
#define MC_COR_ECC_CNT_5	0x94

#define DIMM_TOP_COR_ERR(r)			(((r) >> 16) & 0x7fff)
#define DIMM_BOT_COR_ERR(r)			((r) & 0x7fff)


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	/* OFFSETS for Devices 4,5 and 6 Function 0 */

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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

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#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

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#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

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#define MC_CHANNEL_ADDR_MATCH	0xf0
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#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
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	/* OFFSETS for Devices 4,5 and 6 Function 1 */
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#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
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  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
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  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
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  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
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  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
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#define MC_RANK_PRESENT		0x7c

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#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

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/*
 * i7core structs
 */

#define NUM_CHANS 3
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#define MAX_DIMMS 3		/* Max DIMMS per channel */
#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
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struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
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	u32	ch_map;
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};

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struct i7core_inject {
	int	enable;

	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

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struct i7core_channel {
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	u32		ranks;
	u32		dimms;
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};

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struct pci_id_descr {
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	int			dev;
	int			func;
	int 			dev_id;
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	int			optional;
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};

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struct pci_id_table {
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	const struct pci_id_descr	*descr;
	int				n_devs;
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};

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struct i7core_dev {
	struct list_head	list;
	u8			socket;
	struct pci_dev		**pdev;
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	int			n_devs;
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	struct mem_ctl_info	*mci;
};

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struct i7core_pvt {
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	struct pci_dev	*pci_noncore;
	struct pci_dev	*pci_mcr[MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];

	struct i7core_dev *i7core_dev;
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	struct i7core_info	info;
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	struct i7core_inject	inject;
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	struct i7core_channel	channel[NUM_CHANS];
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	int		ce_count_available;
	int 		csrow_map[NUM_CHANS][MAX_DIMMS];
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			/* ECC corrected errors counts per udimm */
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	unsigned long	udimm_ce_count[MAX_DIMMS];
	int		udimm_last_ce_count[MAX_DIMMS];
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			/* ECC corrected errors counts per rdimm */
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	unsigned long	rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
	int		rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
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	unsigned int	is_registered;
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	/* mcelog glue */
	struct edac_mce		edac_mce;
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	/* Fifo double buffers */
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	struct mce		mce_entry[MCE_LOG_LEN];
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	struct mce		mce_outentry[MCE_LOG_LEN];

	/* Fifo in/out counters */
	unsigned		mce_in, mce_out;

	/* Count indicator to show errors not got */
	unsigned		mce_overrun;
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	/* Struct to control EDAC polling */
	struct edac_pci_ctl_info *i7core_pci;
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};

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#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

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static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
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			/* Exists only for RDIMM */
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	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
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	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
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		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },

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};
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static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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	{ PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
	{ PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
	{ PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },

	{ PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
	{ PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
	{ PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
	{ PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC)   },

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	{ PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
	{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
	{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
	{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
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	/*
	 * This is the PCI device has an alternate address on some
	 * processors like Core i7 860
	 */
	{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
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};

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static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1  },
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },
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		/* Generic Non-core registers */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },

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};

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#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
static const struct pci_id_table pci_dev_table[] = {
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	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
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	{0,}			/* 0 terminated list. */
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};

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/*
 *	pci_device_id	table for which devices we are looking for
 */
static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
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	{0,}			/* 0 terminated list. */
};

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/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
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#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
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	/* MC_STATUS bits */
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#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
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#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
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	/* MC_MAX_DOD read functions */
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static inline int numdimms(u32 dimms)
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{
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	return (dimms & 0x3) + 1;
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}

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static inline int numrank(u32 rank)
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{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

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	return ranks[rank & 0x3];
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}

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static inline int numbank(u32 bank)
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{
	static int banks[4] = { 4, 8, 16, -EINVAL };

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	return banks[bank & 0x3];
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}

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static inline int numrow(u32 row)
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{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

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	return rows[row & 0x7];
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}

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static inline int numcol(u32 col)
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{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
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	return cols[col & 0x3];
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}

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static struct i7core_dev *get_i7core_dev(u8 socket)
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{
	struct i7core_dev *i7core_dev;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
		if (i7core_dev->socket == socket)
			return i7core_dev;
	}

	return NULL;
}

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static struct i7core_dev *alloc_i7core_dev(u8 socket,
					   const struct pci_id_table *table)
{
	struct i7core_dev *i7core_dev;

	i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
	if (!i7core_dev)
		return NULL;

	i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
				   GFP_KERNEL);
	if (!i7core_dev->pdev) {
		kfree(i7core_dev);
		return NULL;
	}

	i7core_dev->socket = socket;
	i7core_dev->n_devs = table->n_devs;
	list_add_tail(&i7core_dev->list, &i7core_edac_list);

	return i7core_dev;
}

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static void free_i7core_dev(struct i7core_dev *i7core_dev)
{
	list_del(&i7core_dev->list);
	kfree(i7core_dev->pdev);
	kfree(i7core_dev);
}

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/****************************************************************************
			Memory check routines
 ****************************************************************************/
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static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
					  unsigned func)
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{
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	struct i7core_dev *i7core_dev = get_i7core_dev(socket);
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	int i;

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	if (!i7core_dev)
		return NULL;

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	for (i = 0; i < i7core_dev->n_devs; i++) {
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		if (!i7core_dev->pdev[i])
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			continue;

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		if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
		    PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
			return i7core_dev->pdev[i];
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		}
	}

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	return NULL;
}

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/**
 * i7core_get_active_channels() - gets the number of channels and csrows
 * @socket:	Quick Path Interconnect socket
 * @channels:	Number of channels that will be returned
 * @csrows:	Number of csrows found
 *
 * Since EDAC core needs to know in advance the number of available channels
 * and csrows, in order to allocate memory for csrows/channels, it is needed
 * to run two similar steps. At the first step, implemented on this function,
 * it checks the number of csrows/channels present at one socket.
 * this is used in order to properly allocate the size of mci components.
 *
 * It should be noticed that none of the current available datasheets explain
 * or even mention how csrows are seen by the memory controller. So, we need
 * to add a fake description for csrows.
 * So, this driver is attributing one DIMM memory for one csrow.
 */
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static int i7core_get_active_channels(const u8 socket, unsigned *channels,
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				      unsigned *csrows)
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{
	struct pci_dev *pdev = NULL;
	int i, j;
	u32 status, control;

	*channels = 0;
	*csrows = 0;

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	pdev = get_pdev_slot_func(socket, 3, 0);
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	if (!pdev) {
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		i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
			      socket);
545
		return -ENODEV;
546
	}
547 548 549 550 551 552

	/* Device 3 function 0 reads */
	pci_read_config_dword(pdev, MC_STATUS, &status);
	pci_read_config_dword(pdev, MC_CONTROL, &control);

	for (i = 0; i < NUM_CHANS; i++) {
553
		u32 dimm_dod[3];
554 555 556 557 558
		/* Check if the channel is active */
		if (!(control & (1 << (8 + i))))
			continue;

		/* Check if the channel is disabled */
559
		if (status & (1 << i))
560 561
			continue;

562
		pdev = get_pdev_slot_func(socket, i + 4, 1);
563
		if (!pdev) {
564 565 566
			i7core_printk(KERN_ERR, "Couldn't find socket %d "
						"fn %d.%d!!!\n",
						socket, i + 4, 1);
567 568 569 570 571 572 573 574 575 576
			return -ENODEV;
		}
		/* Devices 4-6 function 1 */
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM2, &dimm_dod[2]);

577
		(*channels)++;
578 579 580 581 582 583

		for (j = 0; j < 3; j++) {
			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;
			(*csrows)++;
		}
584 585
	}

586
	debugf0("Number of active channels on socket %d: %d\n",
587
		socket, *channels);
588

589 590 591
	return 0;
}

592
static int get_dimm_config(const struct mem_ctl_info *mci)
593 594
{
	struct i7core_pvt *pvt = mci->pvt_info;
595
	struct csrow_info *csr;
596
	struct pci_dev *pdev;
597
	int i, j;
598
	int csrow = 0;
599
	unsigned long last_page = 0;
600
	enum edac_type mode;
601
	enum mem_type mtype;
602

603
	/* Get data from the MC register, function 0 */
604
	pdev = pvt->pci_mcr[0];
605
	if (!pdev)
606 607
		return -ENODEV;

608
	/* Device 3 function 0 reads */
609 610 611 612
	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
613

614
	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
615
		pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
616
		pvt->info.max_dod, pvt->info.ch_map);
617

618
	if (ECC_ENABLED(pvt)) {
619
		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
620 621 622 623 624
		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
625
		debugf0("ECC disabled\n");
626 627
		mode = EDAC_NONE;
	}
628 629

	/* FIXME: need to handle the error codes */
630 631
	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
632 633
		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
634
		numbank(pvt->info.max_dod >> 4),
635 636
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
637

638
	for (i = 0; i < NUM_CHANS; i++) {
639
		u32 data, dimm_dod[3], value[8];
640

641 642 643
		if (!pvt->pci_ch[i][0])
			continue;

644 645 646 647 648 649 650 651 652
		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

653
		/* Devices 4-6 function 0 */
654
		pci_read_config_dword(pvt->pci_ch[i][0],
655 656
				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

657
		pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
658
						4 : 2;
659

660 661
		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
662
		else
663 664
			mtype = MEM_DDR3;
#if 0
665 666 667 668 669 670
		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].dimms = 3;
		else if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].dimms = 1;
		else
			pvt->channel[i].dimms = 2;
671 672 673
#endif

		/* Devices 4-6 function 1 */
674
		pci_read_config_dword(pvt->pci_ch[i][1],
675
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
676
		pci_read_config_dword(pvt->pci_ch[i][1],
677
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
678
		pci_read_config_dword(pvt->pci_ch[i][1],
679
				MC_DOD_CH_DIMM2, &dimm_dod[2]);
680

681
		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
682
			"%d ranks, %cDIMMs\n",
683 684 685
			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
686
			pvt->channel[i].ranks,
687
			(data & REGISTERED_DIMM) ? 'R' : 'U');
688 689 690

		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
691
			u32 size, npages;
692 693 694 695 696 697 698 699 700

			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

701 702 703
			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

704
			pvt->channel[i].dimms++;
705

706 707 708
			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
709 710 711
				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

712
			npages = MiB_TO_PAGES(size);
713

714
			csr = &mci->csrows[csrow];
715 716 717 718 719
			csr->first_page = last_page + 1;
			last_page += npages;
			csr->last_page = last_page;
			csr->nr_pages = npages;

720
			csr->page_mask = 0;
721
			csr->grain = 8;
722
			csr->csrow_idx = csrow;
723 724 725 726
			csr->nr_channels = 1;

			csr->channels[0].chan_idx = i;
			csr->channels[0].ce_count = 0;
727

728
			pvt->csrow_map[i][j] = csrow;
729

730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746
			switch (banks) {
			case 4:
				csr->dtype = DEV_X4;
				break;
			case 8:
				csr->dtype = DEV_X8;
				break;
			case 16:
				csr->dtype = DEV_X16;
				break;
			default:
				csr->dtype = DEV_UNKNOWN;
			}

			csr->edac_mode = mode;
			csr->mtype = mtype;

747
			csrow++;
748
		}
749

750 751 752 753 754 755 756 757
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
758
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
759
		for (j = 0; j < 8; j++)
760
			debugf1("\t\t%#x\t%#x\t%#x\n",
761 762
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
763
				(value[j] & ((1 << 24) - 1)));
764 765
	}

766 767 768
	return 0;
}

769 770 771 772 773 774 775 776 777 778 779
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
780
static int disable_inject(const struct mem_ctl_info *mci)
781 782 783 784 785
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

786
	if (!pvt->pci_ch[pvt->inject.channel][0])
787 788
		return -ENODEV;

789
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
790
				MC_CHANNEL_ERROR_INJECT, 0);
791 792

	return 0;
793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
}

/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
810
		disable_inject(mci);
811 812 813

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
814
		return -EIO;
815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
843
		disable_inject(mci);
844 845 846

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
847
		return -EIO;
848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877

	pvt->inject.type = (u32) value;
	return count;
}

static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
878
		disable_inject(mci);
879 880 881

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
882
		return -EIO;
883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905

	pvt->inject.eccmask = (u32) value;
	return count;
}

static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */

906 907 908 909 910
#define DECLARE_ADDR_MATCH(param, limit)			\
static ssize_t i7core_inject_store_##param(			\
		struct mem_ctl_info *mci,			\
		const char *data, size_t count)			\
{								\
911
	struct i7core_pvt *pvt;					\
912 913 914
	long value;						\
	int rc;							\
								\
915 916 917
	debugf1("%s()\n", __func__);				\
	pvt = mci->pvt_info;					\
								\
918 919 920
	if (pvt->inject.enable)					\
		disable_inject(mci);				\
								\
921
	if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
		value = -1;					\
	else {							\
		rc = strict_strtoul(data, 10, &value);		\
		if ((rc < 0) || (value >= limit))		\
			return -EIO;				\
	}							\
								\
	pvt->inject.param = value;				\
								\
	return count;						\
}								\
								\
static ssize_t i7core_inject_show_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
938 939 940 941
	struct i7core_pvt *pvt;					\
								\
	pvt = mci->pvt_info;					\
	debugf1("%s() pvt=%p\n", __func__, pvt);		\
942 943 944 945
	if (pvt->inject.param < 0)				\
		return sprintf(data, "any\n");			\
	else							\
		return sprintf(data, "%d\n", pvt->inject.param);\
946 947
}

948 949 950 951 952 953 954 955 956
#define ATTR_ADDR_MATCH(param)					\
	{							\
		.attr = {					\
			.name = #param,				\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_inject_show_##param,		\
		.store = i7core_inject_store_##param,		\
	}
957

958 959 960 961 962 963
DECLARE_ADDR_MATCH(channel, 3);
DECLARE_ADDR_MATCH(dimm, 3);
DECLARE_ADDR_MATCH(rank, 4);
DECLARE_ADDR_MATCH(bank, 32);
DECLARE_ADDR_MATCH(page, 0x10000);
DECLARE_ADDR_MATCH(col, 0x4000);
964

965
static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
966 967 968 969
{
	u32 read;
	int count;

970 971 972 973
	debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val);

974 975
	for (count = 0; count < 10; count++) {
		if (count)
976
			msleep(100);
977 978 979 980 981 982 983
		pci_write_config_dword(dev, where, val);
		pci_read_config_dword(dev, where, &read);

		if (read == val)
			return 0;
	}

984 985 986 987
	i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
		"write=%08x. Read=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val, read);
988 989 990 991

	return -EINVAL;
}

992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
				       const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

1019
	if (!pvt->pci_ch[pvt->inject.channel][0])
1020 1021
		return 0;

1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
1035
		mask |= 1LL << 41;
1036
	else {
1037
		if (pvt->channel[pvt->inject.channel].dimms > 2)
1038
			mask |= (pvt->inject.dimm & 0x3LL) << 35;
1039
		else
1040
			mask |= (pvt->inject.dimm & 0x1LL) << 36;
1041 1042 1043 1044
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
1045
		mask |= 1LL << 40;
1046
	else {
1047
		if (pvt->channel[pvt->inject.channel].dimms > 2)
1048
			mask |= (pvt->inject.rank & 0x1LL) << 34;
1049
		else
1050
			mask |= (pvt->inject.rank & 0x3LL) << 34;
1051 1052 1053 1054
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
1055
		mask |= 1LL << 39;
1056
	else
1057
		mask |= (pvt->inject.bank & 0x15LL) << 30;
1058 1059 1060

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
1061
		mask |= 1LL << 38;
1062
	else
1063
		mask |= (pvt->inject.page & 0xffff) << 14;
1064 1065 1066

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
1067
		mask |= 1LL << 37;
1068
	else
1069
		mask |= (pvt->inject.col & 0x3fff);
1070

1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
		     (pvt->inject.type & 0x6) << (3 - 1);

	/* Unlock writes to registers - this register is write only */
1083
	pci_write_config_dword(pvt->pci_noncore,
1084
			       MC_CFG_CONTROL, 0x2);
1085

1086
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1087
			       MC_CHANNEL_ADDR_MATCH, mask);
1088
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1089 1090
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);

1091
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1092 1093
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

1094
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1095
			       MC_CHANNEL_ERROR_INJECT, injectmask);
1096

1097
	/*
1098 1099 1100
	 * This is something undocumented, based on my tests
	 * Without writing 8 to this register, errors aren't injected. Not sure
	 * why.
1101
	 */
1102
	pci_write_config_dword(pvt->pci_noncore,
1103
			       MC_CFG_CONTROL, 8);
1104

1105 1106
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
1107 1108
		mask, pvt->inject.eccmask, injectmask);

1109

1110 1111 1112 1113 1114 1115 1116
	return count;
}

static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
					char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
1117 1118
	u32 injectmask;

1119 1120 1121
	if (!pvt->pci_ch[pvt->inject.channel][0])
		return 0;

1122
	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1123
			       MC_CHANNEL_ERROR_INJECT, &injectmask);
1124 1125 1126 1127 1128 1129

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1130 1131 1132
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
#define DECLARE_COUNTER(param)					\
static ssize_t i7core_show_counter_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
	struct i7core_pvt *pvt = mci->pvt_info;			\
								\
	debugf1("%s() \n", __func__);				\
	if (!pvt->ce_count_available || (pvt->is_registered))	\
		return sprintf(data, "data unavailable\n");	\
	return sprintf(data, "%lu\n",				\
			pvt->udimm_ce_count[param]);		\
}
1146

1147 1148 1149 1150 1151 1152 1153
#define ATTR_COUNTER(param)					\
	{							\
		.attr = {					\
			.name = __stringify(udimm##param),	\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_show_counter_##param		\
1154
	}
1155

1156 1157 1158
DECLARE_COUNTER(0);
DECLARE_COUNTER(1);
DECLARE_COUNTER(2);
1159

1160 1161 1162
/*
 * Sysfs struct
 */
1163

1164
static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1165 1166 1167 1168 1169 1170
	ATTR_ADDR_MATCH(channel),
	ATTR_ADDR_MATCH(dimm),
	ATTR_ADDR_MATCH(rank),
	ATTR_ADDR_MATCH(bank),
	ATTR_ADDR_MATCH(page),
	ATTR_ADDR_MATCH(col),
1171
	{ } /* End of list */
1172 1173
};

1174
static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1175 1176 1177 1178
	.name  = "inject_addrmatch",
	.mcidev_attr = i7core_addrmatch_attrs,
};

1179
static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1180 1181 1182
	ATTR_COUNTER(0),
	ATTR_COUNTER(1),
	ATTR_COUNTER(2),
1183
	{ .attr = { .name = NULL } }
1184 1185
};

1186
static const struct mcidev_sysfs_group i7core_udimm_counters = {
1187 1188 1189 1190
	.name  = "all_channel_counts",
	.mcidev_attr = i7core_udimm_counters_attrs,
};

1191
static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
1214
		.grp = &i7core_inject_addrmatch,
1215 1216 1217 1218 1219 1220 1221 1222
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	},
1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
	{ }	/* End of list */
};

static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
		.grp = &i7core_inject_addrmatch,
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	}, {
		.grp = &i7core_udimm_counters,
	},
	{ }	/* End of list */
1261 1262
};

1263 1264 1265 1266 1267
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
1268
 *	i7core_put_all_devices	'put' all the devices that we have
1269 1270
 *				reserved via 'get'
 */
1271
static void i7core_put_devices(struct i7core_dev *i7core_dev)
1272
{
1273
	int i;
1274

1275
	debugf0(__FILE__ ": %s()\n", __func__);
1276
	for (i = 0; i < i7core_dev->n_devs; i++) {
1277 1278 1279 1280 1281 1282 1283 1284
		struct pci_dev *pdev = i7core_dev->pdev[i];
		if (!pdev)
			continue;
		debugf0("Removing dev %02x:%02x.%d\n",
			pdev->bus->number,
			PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
		pci_dev_put(pdev);
	}
1285
}
1286

1287 1288
static void i7core_put_all_devices(void)
{
1289
	struct i7core_dev *i7core_dev, *tmp;