rtl8723a_hal_init.c 70.6 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
/******************************************************************************
 *
 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/
#define _HAL_INIT_C_

#include <linux/firmware.h>
#include <drv_types.h>
#include <rtw_efuse.h>

#include <rtl8723a_hal.h>
22
#include <usb_ops_linux.h>
23
24
25
26
27
28
29

static void _FWDownloadEnable(struct rtw_adapter *padapter, bool enable)
{
	u8 tmp;

	if (enable) {
		/*  8051 enable */
30
		tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
31
		rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
32
33

		/*  MCU firmware download enable. */
34
		tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
35
		rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
36
37

		/*  8051 reset */
38
		tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
39
		rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
40
41
	} else {
		/*  MCU firmware download disable. */
42
		tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
43
		rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
44
45

		/*  Reserved for fw extension. */
46
		rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
	}
}

static int _BlockWrite(struct rtw_adapter *padapter, void *buffer, u32 buffSize)
{
	int ret = _SUCCESS;
	/*  (Default) Phase #1 : PCI muse use 4-byte write to download FW */
	u32 blockSize_p1 = 4;
	/*  Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
	u32 blockSize_p2 = 8;
	/*  Phase #3 : Use 1-byte, the remnant of FW image. */
	u32 blockSize_p3 = 1;
	u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
	u32 remainSize_p1 = 0, remainSize_p2 = 0;
	u8 *bufferPtr = (u8 *) buffer;
	u32 i = 0, offset = 0;

	blockSize_p1 = 254;

	/* 3 Phase #1 */
	blockCount_p1 = buffSize / blockSize_p1;
	remainSize_p1 = buffSize % blockSize_p1;

	if (blockCount_p1) {
		RT_TRACE(_module_hal_init_c_, _drv_notice_,
			 ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) "
			  "blockCount_p1(%d) remainSize_p1(%d)\n",
			  buffSize, blockSize_p1, blockCount_p1,
			  remainSize_p1));
	}

	for (i = 0; i < blockCount_p1; i++) {
79
80
81
82
		ret = rtl8723au_writeN(padapter, (FW_8723A_START_ADDRESS +
						  i * blockSize_p1),
				       blockSize_p1,
				       (bufferPtr + i * blockSize_p1));
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
		if (ret == _FAIL)
			goto exit;
	}

	/* 3 Phase #2 */
	if (remainSize_p1) {
		offset = blockCount_p1 * blockSize_p1;

		blockCount_p2 = remainSize_p1 / blockSize_p2;
		remainSize_p2 = remainSize_p1 % blockSize_p2;

		if (blockCount_p2) {
			RT_TRACE(_module_hal_init_c_, _drv_notice_,
				 ("_BlockWrite: [P2] buffSize_p2(%d) "
				  "blockSize_p2(%d) blockCount_p2(%d) "
				  "remainSize_p2(%d)\n",
				  (buffSize - offset), blockSize_p2,
				  blockCount_p2, remainSize_p2));
		}

		for (i = 0; i < blockCount_p2; i++) {
104
105
106
107
108
109
			ret = rtl8723au_writeN(padapter,
					       (FW_8723A_START_ADDRESS +
						offset + i * blockSize_p2),
					       blockSize_p2,
					       (bufferPtr + offset +
						i * blockSize_p2));
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

			if (ret == _FAIL)
				goto exit;
		}
	}

	/* 3 Phase #3 */
	if (remainSize_p2) {
		offset = (blockCount_p1 * blockSize_p1) +
			(blockCount_p2 * blockSize_p2);

		blockCount_p3 = remainSize_p2 / blockSize_p3;

		RT_TRACE(_module_hal_init_c_, _drv_notice_,
			 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) "
			  "blockCount_p3(%d)\n",
			  (buffSize - offset), blockSize_p3, blockCount_p3));

		for (i = 0; i < blockCount_p3; i++) {
129
130
131
			ret = rtl8723au_write8(padapter,
					       (FW_8723A_START_ADDRESS + offset + i),
					       *(bufferPtr + offset + i));
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147

			if (ret == _FAIL)
				goto exit;
		}
	}

exit:
	return ret;
}

static int
_PageWrite(struct rtw_adapter *padapter, u32 page, void *buffer, u32 size)
{
	u8 value8;
	u8 u8Page = (u8) (page & 0x07);

148
	value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
149
	rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192

	return _BlockWrite(padapter, buffer, size);
}

static int _WriteFW(struct rtw_adapter *padapter, void *buffer, u32 size)
{
	/*  Since we need dynamic decide method of dwonload fw, so we
	    call this function to get chip version. */
	/*  We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
	int ret = _SUCCESS;
	u32 pageNums, remainSize;
	u32 page, offset;
	u8 *bufferPtr = (u8 *) buffer;

	pageNums = size / MAX_PAGE_SIZE;
	/* RT_ASSERT((pageNums <= 4),
	   ("Page numbers should not greater then 4 \n")); */
	remainSize = size % MAX_PAGE_SIZE;

	for (page = 0; page < pageNums; page++) {
		offset = page * MAX_PAGE_SIZE;
		ret = _PageWrite(padapter, page, bufferPtr + offset,
				 MAX_PAGE_SIZE);

		if (ret == _FAIL)
			goto exit;
	}
	if (remainSize) {
		offset = pageNums * MAX_PAGE_SIZE;
		page = pageNums;
		ret = _PageWrite(padapter, page, bufferPtr + offset,
				 remainSize);

		if (ret == _FAIL)
			goto exit;
	}
	RT_TRACE(_module_hal_init_c_, _drv_info_,
		 ("_WriteFW Done- for Normal chip.\n"));

exit:
	return ret;
}

193
static int _FWFreeToGo(struct rtw_adapter *padapter)
194
195
196
197
198
199
{
	u32 counter = 0;
	u32 value32;

	/*  polling CheckSum report */
	do {
200
		value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
201
202
203
204
205
206
207
208
209
210
211
212
213
214
		if (value32 & FWDL_ChkSum_rpt)
			break;
	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);

	if (counter >= POLLING_READY_TIMEOUT_COUNT) {
		RT_TRACE(_module_hal_init_c_, _drv_err_,
			 ("%s: chksum report fail! REG_MCUFWDL:0x%08x\n",
			  __func__, value32));
		return _FAIL;
	}
	RT_TRACE(_module_hal_init_c_, _drv_info_,
		 ("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__,
		  value32));

215
	value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
216
217
	value32 |= MCUFWDL_RDY;
	value32 &= ~WINTINI_RDY;
218
	rtl8723au_write32(padapter, REG_MCUFWDL, value32);
219
220
221
222

	/*  polling for FW ready */
	counter = 0;
	do {
223
		value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
		if (value32 & WINTINI_RDY) {
			RT_TRACE(_module_hal_init_c_, _drv_info_,
				 ("%s: Polling FW ready success!! "
				  "REG_MCUFWDL:0x%08x\n",
				  __func__, value32));
			return _SUCCESS;
		}
		udelay(5);
	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);

	RT_TRACE(_module_hal_init_c_, _drv_err_,
		 ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
		  __func__, value32));
	return _FAIL;
}

#define IS_FW_81xxC(padapter)	(((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)

void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
	u8 u1bTmp;
	u8 Delay = 100;

	if (!(IS_FW_81xxC(padapter) &&
	      ((pHalData->FirmwareVersion < 0x21) ||
	       (pHalData->FirmwareVersion == 0x21 &&
		pHalData->FirmwareSubVersion < 0x01)))) {
		/*  after 88C Fw v33.1 */
		/* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
254
		rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
255

256
		u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
257
		while (u1bTmp & BIT(2)) {
258
259
260
261
			Delay--;
			if (Delay == 0)
				break;
			udelay(50);
262
			u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
263
264
265
266
267
268
269
		}
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("-%s: 8051 reset success (%d)\n", __func__,
			  Delay));

		if ((Delay == 0)) {
			/* force firmware reset */
270
			u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
271
272
			rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
					 u1bTmp & ~BIT(2));
273
274
275
276
277
278
279
280
281
		}
	}
}

/*  */
/*	Description: */
/*		Download 8192C firmware code. */
/*  */
/*  */
282
int rtl8723a_FirmwareDownload(struct rtw_adapter *padapter)
283
{
284
	int rtStatus = _SUCCESS;
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
	u8 writeFW_retry = 0;
	unsigned long fwdl_start_time;
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
	struct device *device = dvobj_to_dev(dvobj);
	struct rt_8723a_firmware_hdr *pFwHdr = NULL;
	const struct firmware *fw;
	char *fw_name;
	u8 *firmware_buf = NULL;
	u8 *buf;
	int fw_size;
	static int log_version;

	RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));

	if (IS_8723A_A_CUT(pHalData->VersionID)) {
301
		fw_name = "rtlwifi/rtl8723aufw_A.bin";
302
303
304
305
306
307
308
309
310
311
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("rtl8723a_FirmwareDownload: R8723FwImageArray_UMC "
			  "for RTL8723A A CUT\n"));
	} else if (IS_8723A_B_CUT(pHalData->VersionID)) {
		/*  WLAN Fw. */
		if (padapter->registrypriv.wifi_spec == 1) {
			fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
			DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithoutBT for "
				  "RTL8723A B CUT\n");
		} else {
312
313
314
315
316
317
318
319
320
			if (rtl8723a_BT_coexist(padapter)) {
				fw_name = "rtlwifi/rtl8723aufw_B.bin";
				DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithBT "
					  "for RTL8723A B CUT\n");
			} else {
				fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
				DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithout "
					  "BT for RTL8723A B CUT\n");
			}
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
		}
	} else {
		/*  <Roger_TODO> We should download proper RAM Code here
		    to match the ROM code. */
		RT_TRACE(_module_hal_init_c_, _drv_err_,
			 ("%s: unknow version!\n", __func__));
		rtStatus = _FAIL;
		goto Exit;
	}

	pr_info("rtl8723au: Loading firmware %s\n", fw_name);
	if (request_firmware(&fw, fw_name, device)) {
		pr_err("rtl8723au: request_firmware load failed\n");
		rtStatus = _FAIL;
		goto Exit;
	}
	if (!fw) {
		pr_err("rtl8723au: Firmware %s not available\n", fw_name);
		rtStatus = _FAIL;
		goto Exit;
	}
342
	firmware_buf = kmemdup(fw->data, fw->size, GFP_KERNEL);
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
	if (!firmware_buf) {
		rtStatus = _FAIL;
		goto Exit;
	}
	buf = firmware_buf;
	fw_size = fw->size;
	release_firmware(fw);

	/*  To Check Fw header. Added by tynli. 2009.12.04. */
	pFwHdr = (struct rt_8723a_firmware_hdr *)firmware_buf;

	pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
	pHalData->FirmwareSubVersion = pFwHdr->Subversion;
	pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);

	DBG_8723A("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
		  __func__, pHalData->FirmwareVersion,
		  pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);

	if (!log_version++)
		pr_info("%sFirmware Version %d, SubVersion %d, Signature "
			"0x%x\n", DRIVER_PREFIX, pHalData->FirmwareVersion,
			pHalData->FirmwareSubVersion,
			pHalData->FirmwareSignature);

	if (IS_FW_HEADER_EXIST(pFwHdr)) {
		/*  Shift 32 bytes for FW header */
		buf = buf + 32;
		fw_size = fw_size - 32;
	}

	/*  Suggested by Filen. If 8051 is running in RAM code, driver should
	    inform Fw to reset by itself, */
	/*  or it will cause download Fw fail. 2010.02.01. by tynli. */
377
	if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
378
379
		/* 8051 RAM code */
		rtl8723a_FirmwareSelfReset(padapter);
380
		rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
381
382
383
384
385
386
	}

	_FWDownloadEnable(padapter, true);
	fwdl_start_time = jiffies;
	while (1) {
		/* reset the FWDL chksum */
387
388
389
		rtl8723au_write8(padapter, REG_MCUFWDL,
				 rtl8723au_read8(padapter, REG_MCUFWDL) |
				 FWDL_ChkSum_rpt);
390
391
392
393

		rtStatus = _WriteFW(padapter, buf, fw_size);

		if (rtStatus == _SUCCESS ||
394
		    (jiffies_to_msecs(jiffies - fwdl_start_time) > 500 &&
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
		     writeFW_retry++ >= 3))
			break;

		DBG_8723A("%s writeFW_retry:%u, time after fwdl_start_time:"
			  "%ums\n", __func__, writeFW_retry,
			  jiffies_to_msecs(jiffies - fwdl_start_time));
	}
	_FWDownloadEnable(padapter, false);
	if (_SUCCESS != rtStatus) {
		DBG_8723A("DL Firmware failed!\n");
		goto Exit;
	}

	rtStatus = _FWFreeToGo(padapter);
	if (_SUCCESS != rtStatus) {
		RT_TRACE(_module_hal_init_c_, _drv_err_,
			 ("DL Firmware failed!\n"));
		goto Exit;
	}
	RT_TRACE(_module_hal_init_c_, _drv_info_,
		 ("Firmware is ready to run!\n"));

Exit:
	kfree(firmware_buf);
	return rtStatus;
}

void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);

	/*  Init Fw LPS related. */
	padapter->pwrctrlpriv.bFwCurrentInPSMode = false;

	/*  Init H2C counter. by tynli. 2009.12.09. */
	pHalData->LastHMEBoxNum = 0;
}

/*  */
/*				Efuse related code */
/*  */
static u8
hal_EfuseSwitchToBank(struct rtw_adapter *padapter, u8 bank)
{
	u8 bRet = false;
	u32 value32 = 0;

	DBG_8723A("%s: Efuse switch bank to %d\n", __func__, bank);
443
	value32 = rtl8723au_read32(padapter, EFUSE_TEST);
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
	bRet = true;
	switch (bank) {
	case 0:
		value32 = (value32 & ~EFUSE_SEL_MASK) |
			EFUSE_SEL(EFUSE_WIFI_SEL_0);
		break;
	case 1:
		value32 = (value32 & ~EFUSE_SEL_MASK) |
			EFUSE_SEL(EFUSE_BT_SEL_0);
		break;
	case 2:
		value32 = (value32 & ~EFUSE_SEL_MASK) |
			EFUSE_SEL(EFUSE_BT_SEL_1);
		break;
	case 3:
		value32 = (value32 & ~EFUSE_SEL_MASK) |
			EFUSE_SEL(EFUSE_BT_SEL_2);
		break;
	default:
		value32 = (value32 & ~EFUSE_SEL_MASK) |
			EFUSE_SEL(EFUSE_WIFI_SEL_0);
		bRet = false;
		break;
	}
468
	rtl8723au_write32(padapter, EFUSE_TEST, value32);
469
470
471
472
473
474
475
476
477
478
479
480
481

	return bRet;
}

static void
hal_ReadEFuse_WiFi(struct rtw_adapter *padapter,
		   u16 _offset, u16 _size_byte, u8 *pbuf)
{
	u8 *efuseTbl = NULL;
	u16 eFuse_Addr = 0;
	u8 offset, wden;
	u8 efuseHeader, efuseExtHdr, efuseData;
	u16 i, total, used;
482
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
483
484
485
486
487
488
489
490
491

	/*  Do NOT excess total size of EFuse table.
	    Added by Roger, 2008.11.10. */
	if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) {
		DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
			  __func__, _offset, _size_byte);
		return;
	}

492
	efuseTbl = kmalloc(EFUSE_MAP_LEN_8723A, GFP_KERNEL);
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
	if (efuseTbl == NULL) {
		DBG_8723A("%s: alloc efuseTbl fail!\n", __func__);
		return;
	}
	/*  0xff will be efuse default value instead of 0x00. */
	memset(efuseTbl, 0xFF, EFUSE_MAP_LEN_8723A);

	/*  switch bank back to bank 0 for later BT and wifi use. */
	hal_EfuseSwitchToBank(padapter, 0);

	while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
		ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
		if (efuseHeader == 0xFF) {
			DBG_8723A("%s: data end at address =%#x\n", __func__,
				  eFuse_Addr);
			break;
		}

		/*  Check PG header for section num. */
		if (EXT_HEADER(efuseHeader)) {	/* extended header */
			offset = GET_HDR_OFFSET_2_0(efuseHeader);

			ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseExtHdr);
			if (ALL_WORDS_DISABLED(efuseExtHdr)) {
				continue;
			}

			offset |= ((efuseExtHdr & 0xF0) >> 1);
			wden = (efuseExtHdr & 0x0F);
		} else {
			offset = ((efuseHeader >> 4) & 0x0f);
			wden = (efuseHeader & 0x0f);
		}

		if (offset < EFUSE_MAX_SECTION_8723A) {
			u16 addr;
			/*  Get word enable value from PG header */

			addr = offset * PGPKT_DATA_SIZE;
			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
				/* Check word enable condition in the section */
				if (!(wden & (0x01 << i))) {
					ReadEFuseByte23a(padapter, eFuse_Addr++,
						      &efuseData);
					efuseTbl[addr] = efuseData;

					ReadEFuseByte23a(padapter, eFuse_Addr++,
						      &efuseData);
					efuseTbl[addr + 1] = efuseData;
				}
				addr += 2;
			}
		} else {
			DBG_8723A(KERN_ERR "%s: offset(%d) is illegal!!\n",
				  __func__, offset);
			eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
		}
	}

	/*  Copy from Efuse map to output pointer memory!!! */
	for (i = 0; i < _size_byte; i++)
		pbuf[i] = efuseTbl[_offset + i];

	/*  Calculate Efuse utilization */
	EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
				 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
	used = eFuse_Addr - 1;
560
	pHalData->EfuseUsedBytes = used;
561
562
563
564
565
566
567
568
569
570
571
572
573
574

	kfree(efuseTbl);
}

static void
hal_ReadEFuse_BT(struct rtw_adapter *padapter,
		 u16 _offset, u16 _size_byte, u8 *pbuf)
{
	u8 *efuseTbl;
	u8 bank;
	u16 eFuse_Addr;
	u8 efuseHeader, efuseExtHdr, efuseData;
	u8 offset, wden;
	u16 i, total, used;
575
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676

	/*  Do NOT excess total size of EFuse table.
	    Added by Roger, 2008.11.10. */
	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
		DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
			  __func__, _offset, _size_byte);
		return;
	}

	efuseTbl = kmalloc(EFUSE_BT_MAP_LEN, GFP_KERNEL);
	if (efuseTbl == NULL) {
		DBG_8723A("%s: efuseTbl malloc fail!\n", __func__);
		return;
	}
	/*  0xff will be efuse default value instead of 0x00. */
	memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);

	EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
				 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total);

	for (bank = 1; bank < EFUSE_MAX_BANK; bank++) {
		if (hal_EfuseSwitchToBank(padapter, bank) == false) {
			DBG_8723A("%s: hal_EfuseSwitchToBank Fail!!\n",
				  __func__);
			goto exit;
		}

		eFuse_Addr = 0;

		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
			ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
			if (efuseHeader == 0xFF)
				break;

			/*  Check PG header for section num. */
			if (EXT_HEADER(efuseHeader)) {	/* extended header */
				offset = GET_HDR_OFFSET_2_0(efuseHeader);

				ReadEFuseByte23a(padapter, eFuse_Addr++,
					      &efuseExtHdr);
				if (ALL_WORDS_DISABLED(efuseExtHdr)) {
					continue;
				}

				offset |= ((efuseExtHdr & 0xF0) >> 1);
				wden = (efuseExtHdr & 0x0F);
			} else {
				offset = ((efuseHeader >> 4) & 0x0f);
				wden = (efuseHeader & 0x0f);
			}

			if (offset < EFUSE_BT_MAX_SECTION) {
				u16 addr;

				/*  Get word enable value from PG header */

				addr = offset * PGPKT_DATA_SIZE;
				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
					/*  Check word enable condition in
					    the section */
					if (!(wden & (0x01 << i))) {
						ReadEFuseByte23a(padapter,
							      eFuse_Addr++,
							      &efuseData);
						efuseTbl[addr] = efuseData;

						ReadEFuseByte23a(padapter,
							      eFuse_Addr++,
							      &efuseData);
						efuseTbl[addr + 1] = efuseData;
					}
					addr += 2;
				}
			} else {
				DBG_8723A(KERN_ERR
					  "%s: offset(%d) is illegal!!\n",
					  __func__, offset);
				eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
			}
		}

		if ((eFuse_Addr - 1) < total) {
			DBG_8723A("%s: bank(%d) data end at %#x\n",
				  __func__, bank, eFuse_Addr - 1);
			break;
		}
	}

	/*  switch bank back to bank 0 for later BT and wifi use. */
	hal_EfuseSwitchToBank(padapter, 0);

	/*  Copy from Efuse map to output pointer memory!!! */
	for (i = 0; i < _size_byte; i++)
		pbuf[i] = efuseTbl[_offset + i];

	/*  */
	/*  Calculate Efuse utilization. */
	/*  */
	EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
				 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
	used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
677
	pHalData->BTEfuseUsedBytes = used;
678
679
680
681
682

exit:
	kfree(efuseTbl);
}

683
684
685
void
rtl8723a_readefuse(struct rtw_adapter *padapter,
		   u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf)
686
687
688
689
690
691
692
{
	if (efuseType == EFUSE_WIFI)
		hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf);
	else
		hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf);
}

693
u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter)
694
695
696
697
{
	u16 efuse_addr = 0;
	u8 hoffset = 0, hworden = 0;
	u8 efuse_data, word_cnts = 0;
698
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
699

700
	efuse_addr = pHalData->EfuseUsedBytes;
701
702
703
704
705
706
707
708

	DBG_8723A("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);

	/*  switch bank back to bank 0 for later BT and wifi use. */
	hal_EfuseSwitchToBank(padapter, 0);

	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
		if (efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data) ==
709
		    _FAIL) {
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
			DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail! "
				  "addr = 0x%X !!\n", __func__, efuse_addr);
			break;
		}

		if (efuse_data == 0xFF)
			break;

		if (EXT_HEADER(efuse_data)) {
			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
			efuse_addr++;
			efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data);
			if (ALL_WORDS_DISABLED(efuse_data)) {
				continue;
			}

			hoffset |= ((efuse_data & 0xF0) >> 1);
			hworden = efuse_data & 0x0F;
		} else {
			hoffset = (efuse_data >> 4) & 0x0F;
			hworden = efuse_data & 0x0F;
		}

		word_cnts = Efuse_CalculateWordCnts23a(hworden);
		efuse_addr += (word_cnts * 2) + 1;
	}

737
	pHalData->EfuseUsedBytes = efuse_addr;
738
739
740
741
742
743

	DBG_8723A("%s: CurrentSize =%d\n", __func__, efuse_addr);

	return efuse_addr;
}

744
u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter)
745
746
747
748
749
750
751
{
	u16 btusedbytes;
	u16 efuse_addr;
	u8 bank, startBank;
	u8 hoffset = 0, hworden = 0;
	u8 efuse_data, word_cnts = 0;
	u16 retU2 = 0;
752
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
753

754
	btusedbytes = pHalData->BTEfuseUsedBytes;
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779

	efuse_addr = (u16) ((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
	startBank = (u8) (1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));

	DBG_8723A("%s: start from bank =%d addr = 0x%X\n", __func__, startBank,
		  efuse_addr);

	EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
				 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2);

	for (bank = startBank; bank < EFUSE_MAX_BANK; bank++) {
		if (hal_EfuseSwitchToBank(padapter, bank) == false) {
			DBG_8723A(KERN_ERR "%s: switch bank(%d) Fail!!\n",
				  __func__, bank);
			bank = EFUSE_MAX_BANK;
			break;
		}

		/*  only when bank is switched we have to reset
		    the efuse_addr. */
		if (bank != startBank)
			efuse_addr = 0;

		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
			if (efuse_OneByteRead23a(padapter, efuse_addr,
780
					      &efuse_data) == _FAIL) {
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
				DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail!"
					  " addr = 0x%X !!\n",
					  __func__, efuse_addr);
				bank = EFUSE_MAX_BANK;
				break;
			}

			if (efuse_data == 0xFF)
				break;

			if (EXT_HEADER(efuse_data)) {
				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
				efuse_addr++;
				efuse_OneByteRead23a(padapter, efuse_addr,
						  &efuse_data);
				if (ALL_WORDS_DISABLED(efuse_data)) {
					efuse_addr++;
					continue;
				}

				hoffset |= ((efuse_data & 0xF0) >> 1);
				hworden = efuse_data & 0x0F;
			} else {
				hoffset = (efuse_data >> 4) & 0x0F;
				hworden = efuse_data & 0x0F;
			}
			word_cnts = Efuse_CalculateWordCnts23a(hworden);
			/* read next header */
			efuse_addr += (word_cnts * 2) + 1;
		}

		/*  Check if we need to check next bank efuse */
		if (efuse_addr < retU2) {
			break;	/*  don't need to check next bank. */
		}
	}

	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
819
	pHalData->BTEfuseUsedBytes = retU2;
820
821
822
823
824

	DBG_8723A("%s: CurrentSize =%d\n", __func__, retU2);
	return retU2;
}

825
826
bool
rtl8723a_EfusePgPacketRead(struct rtw_adapter *padapter, u8 offset, u8 *data)
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
{
	u8 efuse_data, word_cnts = 0;
	u16 efuse_addr = 0;
	u8 hoffset = 0, hworden = 0;
	u8 i;
	u8 max_section = 0;
	s32 ret;

	if (data == NULL)
		return false;

	EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION,
				 &max_section);
	if (offset > max_section) {
		DBG_8723A("%s: Packet offset(%d) is illegal(>%d)!\n",
			  __func__, offset, max_section);
		return false;
	}

	memset(data, 0xFF, PGPKT_DATA_SIZE);
	ret = true;

	/*  */
	/*  <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the
	    end of Efuse by CP. */
	/*  Skip dummy parts to prevent unexpected data read from Efuse. */
	/*  By pass right now. 2009.02.19. */
	/*  */
	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
		if (efuse_OneByteRead23a(padapter, efuse_addr++, &efuse_data) ==
857
		    _FAIL) {
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
			ret = false;
			break;
		}

		if (efuse_data == 0xFF)
			break;

		if (EXT_HEADER(efuse_data)) {
			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
			efuse_OneByteRead23a(padapter, efuse_addr++, &efuse_data);
			if (ALL_WORDS_DISABLED(efuse_data)) {
				DBG_8723A("%s: Error!! All words disabled!\n",
					  __func__);
				continue;
			}

			hoffset |= ((efuse_data & 0xF0) >> 1);
			hworden = efuse_data & 0x0F;
		} else {
			hoffset = (efuse_data >> 4) & 0x0F;
			hworden = efuse_data & 0x0F;
		}

		if (hoffset == offset) {
			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
				/* Check word enable condition in the section */
				if (!(hworden & (0x01 << i))) {
					ReadEFuseByte23a(padapter, efuse_addr++,
						      &efuse_data);
					data[i * 2] = efuse_data;

					ReadEFuseByte23a(padapter, efuse_addr++,
						      &efuse_data);
					data[(i * 2) + 1] = efuse_data;
				}
			}
		} else {
			word_cnts = Efuse_CalculateWordCnts23a(hworden);
			efuse_addr += word_cnts * 2;
		}
	}

	return ret;
}

903
void rtl8723a_read_chip_version(struct rtw_adapter *padapter)
904
905
906
907
908
909
910
{
	u32 value32;
	struct hal_version ChipVersion;
	struct hal_data_8723a *pHalData;

	pHalData = GET_HAL_DATA(padapter);

911
	value32 = rtl8723au_read32(padapter, REG_SYS_CFG);
912
913
914
915
916
917
918
919
920
921
922
	ChipVersion.ICType = CHIP_8723A;
	ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
	ChipVersion.RFType = RF_TYPE_1T1R;
	ChipVersion.VendorType =
		((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
	ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT;	/*  IC version (CUT) */

	/*  For regulator mode. by tynli. 2011.01.14 */
	pHalData->RegulatorMode = ((value32 & SPS_SEL) ?
				   RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);

923
	value32 = rtl8723au_read32(padapter, REG_GPIO_OUTSTS);
924
925
926
927
928
	/*  ROM code version. */
	ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20);

	/*  For multi-function consideration. Added by Roger, 2010.10.06. */
	pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
929
	value32 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
	pHalData->MultiFunc |=
		((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
	pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
	pHalData->MultiFunc |=
		((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
	pHalData->PolarityCtl =
		((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT :
		 RT_POLARITY_LOW_ACT);
	dump_chip_info23a(ChipVersion);
	pHalData->VersionID = ChipVersion;

	if (IS_1T2R(ChipVersion))
		pHalData->rf_type = RF_1T2R;
	else if (IS_2T2R(ChipVersion))
		pHalData->rf_type = RF_2T2R;
	else
		pHalData->rf_type = RF_1T1R;

	MSG_8723A("RF_Type is %x!!\n", pHalData->rf_type);
}

/*  */
/*  */
/*  20100209 Joseph: */
/*  This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
/*  We just reserve the value of the register in variable
    pHalData->RegBcnCtrlVal and then operate */
/*  the value of the register via atomic operation. */
/*  This prevents from race condition when setting this register. */
/*  The value of pHalData->RegBcnCtrlVal is initialized in
    HwConfigureRTL8192CE() function. */
/*  */
void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits)
{
	struct hal_data_8723a *pHalData;
	u32 addr;
	u8 *pRegBcnCtrlVal;

	pHalData = GET_HAL_DATA(padapter);
	pRegBcnCtrlVal = (u8 *)&pHalData->RegBcnCtrlVal;

	addr = REG_BCN_CTRL;

973
	*pRegBcnCtrlVal = rtl8723au_read8(padapter, addr);
974
975
976
	*pRegBcnCtrlVal |= SetBits;
	*pRegBcnCtrlVal &= ~ClearBits;

977
	rtl8723au_write8(padapter, addr, *pRegBcnCtrlVal);
978
979
980
981
982
983
}

void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);

984
	rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
985
986
987
	pHalData->RegBcnCtrlVal = 0x1010;

	/*  TODO: Remove these magic number */
988
	rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);	/*  ms */
989
990
991
	/*  Firmware will control REG_DRVERLYINT when power saving is enable, */
	/*  so don't set this register on STA mode. */
	if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
992
993
		rtl8723au_write8(padapter, REG_DRVERLYINT,
				 DRIVER_EARLY_INT_TIME);
994
	/*  2ms */
995
	rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
996
997
998
999

	/*  Suggested by designer timchen. Change beacon AIFS to the
	    largest number beacause test chip does not contension before
	    sending beacon. by tynli. 2009.11.03 */
1000
	rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
}

static void ResumeTxBeacon(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);

	/*  2010.03.01. Marked by tynli. No need to call workitem beacause
	    we record the value */
	/*  which should be read from register to a global variable. */

	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));

	pHalData->RegFwHwTxQCtrl |= BIT(6);
1014
1015
1016
	rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
			 pHalData->RegFwHwTxQCtrl);
	rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
1017
	pHalData->RegReg542 |= BIT(0);
1018
	rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
}

static void StopTxBeacon(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);

	/*  2010.03.01. Marked by tynli. No need to call workitem beacause
	    we record the value */
	/*  which should be read from register to a global variable. */

	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));

	pHalData->RegFwHwTxQCtrl &= ~BIT(6);
1032
1033
1034
	rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
			 pHalData->RegFwHwTxQCtrl);
	rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
1035
	pHalData->RegReg542 &= ~BIT(0);
1036
	rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
1037
1038
1039
1040
1041
1042
1043
1044
1045

	CheckFwRsvdPageContent23a(padapter); /*  2010.06.23. Added by tynli. */
}

static void _BeaconFunctionEnable(struct rtw_adapter *padapter, u8 Enable,
				  u8 Linked)
{
	SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
		      0);
1046
	rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
1047
1048
}

1049
void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
{
	u32 value32;
	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;

	/* reset TSF, enable update TSF, correcting TSF On Beacon */

	/* REG_BCN_INTERVAL */
	/* REG_BCNDMATIM */
	/* REG_ATIMWND */
	/* REG_TBTT_PROHIBIT */
	/* REG_DRVERLYINT */
	/* REG_BCN_MAX_ERR */
	/* REG_BCNTCFG (0x510) */
	/* REG_DUAL_TSF_RST */
	/* REG_BCN_CTRL (0x550) */

	/*  */
	/*  ATIM window */
	/*  */
1070
	rtl8723au_write16(padapter, REG_ATIMWND, 2);
1071
1072
1073
1074

	/*  */
	/*  Beacon interval (in unit of TU). */
	/*  */
1075
	rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
1076
1077
1078

	rtl8723a_InitBeaconParameters(padapter);

1079
	rtl8723au_write8(padapter, REG_SLOT, 0x09);
1080
1081
1082
1083

	/*  */
	/*  Reset TSF Timer to zero, added by Roger. 2008.06.24 */
	/*  */
1084
	value32 = rtl8723au_read32(padapter, REG_TCR);
1085
	value32 &= ~TSFRST;
1086
	rtl8723au_write32(padapter, REG_TCR, value32);
1087
1088

	value32 |= TSFRST;
1089
	rtl8723au_write32(padapter, REG_TCR, value32);
1090
1091
1092
1093

	/*  NOTE: Fix test chip's bug (about contention windows's randomness) */
	if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
			  WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
1094
1095
		rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
		rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
1096
1097
1098
1099
1100
1101
1102
1103
	}

	_BeaconFunctionEnable(padapter, true, true);

	ResumeTxBeacon(padapter);
	SetBcnCtrlReg23a(padapter, DIS_BCNQ_SUB, 0);
}

1104
1105
1106
void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
			   enum hal_odm_variable eVariable,
			   void *pValue1, bool bSet)
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
	struct dm_odm_t *podmpriv = &pHalData->odmpriv;
	switch (eVariable) {
	case HAL_ODM_STA_INFO:
	{
		struct sta_info *psta = (struct sta_info *)pValue1;

		if (bSet) {
			DBG_8723A("Set STA_(%d) info\n", psta->mac_id);
			ODM_CmnInfoPtrArrayHook23a(podmpriv,
						ODM_CMNINFO_STA_STATUS,
						psta->mac_id, psta);
		} else {
			DBG_8723A("Clean STA_(%d) info\n", psta->mac_id);
				ODM_CmnInfoPtrArrayHook23a(podmpriv,
							ODM_CMNINFO_STA_STATUS,
							psta->mac_id, NULL);
		}
	}
		break;
	case HAL_ODM_P2P_STATE:
		ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
		break;
	case HAL_ODM_WIFI_DISPLAY_STATE:
		ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
		break;
	default:
		break;
	}
}

1139
void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable)
1140
1141
1142
{
	if (enable) {
		DBG_8723A("Enable notch filter\n");
1143
1144
1145
		rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
				 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
				 BIT(1));
1146
1147
	} else {
		DBG_8723A("Disable notch filter\n");
1148
1149
1150
		rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
			   rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
				 ~BIT(1));
1151
1152
1153
	}
}

1154
bool c2h_id_filter_ccx_8723a(u8 id)
1155
{
1156
	bool ret = false;
1157
1158
1159
1160
1161
1162
	if (id == C2H_CCX_TX_RPT)
		ret = true;

	return ret;
}

1163
int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
1164
{
1165
	int ret = _SUCCESS;
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
	u8 i = 0;

	if (c2h_evt == NULL) {
		DBG_8723A("%s c2h_evt is NULL\n", __func__);
		ret = _FAIL;
		goto exit;
	}

	switch (c2h_evt->id) {
	case C2H_DBG:
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("C2HCommandHandler: %s\n", c2h_evt->payload));
		break;

	case C2H_CCX_TX_RPT:
		handle_txrpt_ccx_8723a(padapter, c2h_evt->payload);
		break;
	case C2H_EXT_RA_RPT:
		break;
	case C2H_HW_INFO_EXCH:
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("[BT], C2H_HW_INFO_EXCH\n"));
		for (i = 0; i < c2h_evt->plen; i++) {
			RT_TRACE(_module_hal_init_c_, _drv_info_,
				 ("[BT], tmpBuf[%d]= 0x%x\n", i,
				  c2h_evt->payload[i]));
		}
		break;

	case C2H_C2H_H2C_TEST:
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("[BT], C2H_H2C_TEST\n"));
		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("[BT], tmpBuf[0]/[1]/[2]/[3]/[4]= 0x%x/ 0x%x/ "
			  "0x%x/ 0x%x/ 0x%x\n", c2h_evt->payload[0],
			  c2h_evt->payload[1], c2h_evt->payload[2],
			  c2h_evt->payload[3], c2h_evt->payload[4]));
		break;

	case C2H_BT_INFO:
		DBG_8723A("%s ,  Got  C2H_BT_INFO \n", __func__);
1207
1208
		rtl8723a_fw_c2h_BT_info(padapter,
					c2h_evt->payload, c2h_evt->plen);
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
		break;

	default:
		ret = _FAIL;
		break;
	}

exit:
	return ret;
}

void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter)
{
	u8 val;

1224
	val = rtl8723au_read8(padapter, REG_LEDCFG2);
1225
1226
	/*  Let 8051 take control antenna settting */
	val |= BIT(7);		/*  DPDT_SEL_EN, 0x4C[23] */
1227
	rtl8723au_write8(padapter, REG_LEDCFG2, val);
1228
1229
1230
1231
1232
1233
}

void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
{
	u8 val;

1234
	val = rtl8723au_read8(padapter, REG_LEDCFG2);
1235
1236
1237
	/*  Let 8051 take control antenna settting */
	if (!(val & BIT(7))) {
		val |= BIT(7);	/*  DPDT_SEL_EN, 0x4C[23] */
1238
		rtl8723au_write8(padapter, REG_LEDCFG2, val);
1239
1240
1241
1242
1243
1244
1245
	}
}

void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter)
{
	u8 val;

1246
	val = rtl8723au_read8(padapter, REG_LEDCFG2);
1247
1248
	/*  Let 8051 take control antenna settting */
	val &= ~BIT(7);		/*  DPDT_SEL_EN, clear 0x4C[23] */
1249
	rtl8723au_write8(padapter, REG_LEDCFG2, val);
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
}

void rtl8723a_init_default_value(struct rtw_adapter *padapter)
{
	struct hal_data_8723a *pHalData;
	struct dm_priv *pdmpriv;
	u8 i;

	pHalData = GET_HAL_DATA(padapter);
	pdmpriv = &pHalData->dmpriv;

	/*  init default value */
	pHalData->fw_ractrl = false;
	pHalData->bIQKInitialized = false;
	if (!padapter->pwrctrlpriv.bkeepfwalive)
		pHalData->LastHMEBoxNum = 0;

	pHalData->bIQKInitialized = false;

	/*  init dm default value */
	pdmpriv->TM_Trigger = 0;	/* for IQK */
/*	pdmpriv->binitialized = false; */
/*	pdmpriv->prv_traffic_idx = 3; */
/*	pdmpriv->initialize = 0; */

	pdmpriv->ThermalValue_HP_index = 0;
	for (i = 0; i < HP_THERMAL_NUM; i++)
		pdmpriv->ThermalValue_HP[i] = 0;

	/*  init Efuse variables */
	pHalData->EfuseUsedBytes = 0;
	pHalData->BTEfuseUsedBytes = 0;
}

u8 GetEEPROMSize8723A(struct rtw_adapter *padapter)
{
	u8 size = 0;
	u32 cr;

1289
	cr = rtl8723au_read16(padapter, REG_9346CR);
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
	/*  6: EEPROM used is 93C46, 4: boot from E-Fuse. */
	size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;

	MSG_8723A("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");

	return size;
}

/*  */
/*  */
/*  LLT R/W/Init function */
/*  */
/*  */
1303
static int _LLTWrite(struct rtw_adapter *padapter, u32 address, u32 data)
1304
{
1305
	int status = _SUCCESS;
1306
1307
1308
1309
1310
	s32 count = 0;
	u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
		    _LLT_OP(_LLT_WRITE_ACCESS);
	u16 LLTReg = REG_LLT_INIT;

1311
	rtl8723au_write32(padapter, LLTReg, value);
1312
1313
1314

	/* polling */
	do {
1315
		value = rtl8723au_read32(padapter, LLTReg);
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
			break;
		}

		if (count > POLLING_LLT_THRESHOLD) {
			RT_TRACE(_module_hal_init_c_, _drv_err_,
				 ("Failed to polling write LLT done at "
				  "address %d!\n", address));
			status = _FAIL;
			break;
		}
	} while (count++);

	return status;
}

1332
int InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary)
1333
{
1334
	int status = _SUCCESS;
1335
1336
1337
1338
1339
1340
	u32 i;
	u32 txpktbuf_bndy = boundary;
	u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;

	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
		status = _LLTWrite(padapter, i, i + 1);
1341
		if (status != _SUCCESS) {
1342
1343
1344
1345
1346
1347
			return status;
		}
	}

	/*  end of list */
	status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1348
	if (status != _SUCCESS) {
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
		return status;
	}

	/*  Make the other pages as ring buffer */
	/*  This ring buffer is used as beacon buffer if we config this
	    MAC as two MAC transfer. */
	/*  Otherwise used as local loopback buffer. */
	for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
		status = _LLTWrite(padapter, i, (i + 1));
		if (_SUCCESS != status) {
			return status;
		}
	}

	/*  Let last entry point to the start entry of ring buffer */
	status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1365
	if (status != _SUCCESS) {
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
		return status;
	}

	return status;
}

static void _DisableGPIO(struct rtw_adapter *padapter)
{
/***************************************
j. GPIO_PIN_CTRL 0x44[31:0]= 0x000
k.Value = GPIO_PIN_CTRL[7:0]
l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
n. LEDCFG 0x4C[15:0] = 0x8080
***************************************/
	u32 value32;
	u32 u4bTmp;

	/* 1. Disable GPIO[7:0] */
1385
	rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
1386
	value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1387
1388
	u4bTmp = value32 & 0x000000FF;
	value32 |= ((u4bTmp << 8) | 0x00FF0000);
1389
	rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399

	/*  */
	/*  <Roger_Notes> For RTL8723u multi-function configuration which
	    was autoload from Efuse offset 0x0a and 0x0b, */
	/*  WLAN HW GPIO[9], GPS HW GPIO[10] and BT HW GPIO[11]. */
	/*  Added by Roger, 2010.10.07. */
	/*  */
	/* 2. Disable GPIO[8] and GPIO[12] */

	/*  Configure all pins as input mode. */
1400
	rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
1401
	value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
1402
1403
1404
	u4bTmp = value32 & 0x0000001F;
	/*  Set pin 8, 10, 11 and pin 12 to output mode. */
	value32 |= ((u4bTmp << 8) | 0x001D0000);
1405
	rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
1406
1407

	/* 3. Disable LED0 & 1 */
1408
	rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
}				/* end of _DisableGPIO() */

static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
{
/**************************************
a.	TXPAUSE 0x522[7:0] = 0xFF		Pause MAC TX queue
b.	RF path 0 offset 0x00 = 0x00		disable RF
c.	APSD_CTRL 0x600[7:0] = 0x40
d.	SYS_FUNC_EN 0x02[7:0] = 0x16		reset BB state machine
e.	SYS_FUNC_EN 0x02[7:0] = 0x14		reset BB state machine
***************************************/
	u8 eRFPath = 0, value8 = 0;

1422
	rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
1423
1424
1425
1426

	PHY_SetRFReg(padapter, (enum RF_RADIO_PATH) eRFPath, 0x0, bMaskByte0, 0x0);

	value8 |= APSDOFF;
1427
	rtl8723au_write8(padapter, REG_APSD_CTRL, value8);	/* 0x40 */
1428
1429
1430
1431

	/*  Set BB reset at first */
	value8 = 0;
	value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1432
	rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8);	/* 0x16 */
1433
1434
1435

	/*  Set global reset. */
	value8 &= ~FEN_BB_GLB_RSTn;
1436
	rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8);	/* 0x14 */
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462

	/*  2010/08/12 MH We need to set BB/GLBAL reset to save power
	    for SS mode. */

/*	RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); */
}

static void _DisableRFAFEAndResetBB(struct rtw_adapter *padapter)
{
	_DisableRFAFEAndResetBB8192C(padapter);
}

static void _ResetDigitalProcedure1_92C(struct rtw_adapter *padapter,
					bool bWithoutHWSM)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);

	if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) {
	/*****************************
	f.	MCUFWDL 0x80[7:0]= 0		reset MCU ready status
	g.	SYS_FUNC_EN 0x02[10]= 0		reset MCU register, (8051 reset)
	h.	SYS_FUNC_EN 0x02[15-12]= 5	reset MAC register, DCORE
	i.     SYS_FUNC_EN 0x02[10]= 1		enable MCU register,
						(8051 enable)
	******************************/
		u16 valu16 = 0;
1463
		rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1464

1465
		valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1466
		/* reset MCU , 8051 */
1467
1468
		rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
				  valu16 & (~FEN_CPUEN));
1469

1470
		valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
1471
1472
1473
		/* reset MAC */
		rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
				  valu16 | (FEN_HWPDN | FEN_ELDR));
1474

1475
		valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1476
		/* enable MCU , 8051 */
1477
1478
		rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
				  valu16 | FEN_CPUEN);
1479
1480
1481
1482
1483
1484
1485
1486
	} else {
		u8 retry_cnts = 0;

		/*  2010/08/12 MH For USB SS, we can not stop 8051 when we
		    are trying to enter IPS/HW&SW radio off. For
		    S3/S4/S5/Disable, we can stop 8051 because */
		/*  we will init FW when power on again. */
		/*  If we want to SS mode, we can not reset 8051. */
1487
		if (rtl8723au_read8(padapter, REG_MCUFWDL) & BIT(1)) {
1488
1489
1490
1491
1492
			/* IF fw in RAM code, do reset */
			if (padapter->bFWReady) {
				/*  2010/08/25 MH Accordign to RD alfred's
				    suggestion, we need to disable other */
				/*  HRCV INT to influence 8051 reset. */
1493
				rtl8723au_write8(padapter, REG_FWIMR, 0x20);
1494
1495
1496
				/*  2011/02/15 MH According to Alex's
				    suggestion, close mask to prevent
				    incorrect FW write operation. */
1497
1498
				rtl8723au_write8(padapter, REG_FTIMR, 0x00);
				rtl8723au_write8(padapter, REG_FSIMR, 0x00);
1499
1500

				/* 8051 reset by self */
1501
1502
				rtl8723au_write8(padapter, REG_HMETFR + 3,
						 0x20);
1503
1504
1505

				while ((retry_cnts++ < 100) &&
				       (FEN_CPUEN &
1506
1507
					rtl8723au_read16(padapter,
							 REG_SYS_FUNC_EN))) {
1508
1509
1510
1511
1512
					udelay(50);	/* us */
				}

				if (retry_cnts >= 100) {
					/* Reset MAC and Enable 8051 */
1513
1514
1515
					rtl8723au_write8(padapter,
							 REG_SYS_FUNC_EN + 1,
							 0x50);
1516
1517
1518
1519
1520
					mdelay(10);
				}
			}
		}
		/* Reset MAC and Enable 8051 */
1521
1522
		rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
		rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
	}

	if (bWithoutHWSM) {
	/*****************************
		Without HW auto state machine
	g.	SYS_CLKR 0x08[15:0] = 0x30A3		disable MAC clock
	h.	AFE_PLL_CTRL 0x28[7:0] = 0x80		disable AFE PLL
	i.	AFE_XTAL_CTRL 0x24[15:0] = 0x880F	gated AFE DIG_CLOCK
	j.	SYS_ISO_CTRL 0x00[7:0] = 0xF9		isolated digital to PON
	******************************/
		/* modify to 0x70A3 by Scott. */
1534
1535
1536
1537
		rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
		rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
		rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
		rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
1538
1539
	} else {
		/*  Disable all RF/BB power */
1540
		rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
	}
}

static void _ResetDigitalProcedure1(struct rtw_adapter *padapter,
				    bool bWithoutHWSM)
{
	_ResetDigitalProcedure1_92C(padapter, bWithoutHWSM);
}

static void _ResetDigitalProcedure2(struct rtw_adapter *padapter)
{
/*****************************
k.	SYS_FUNC_EN 0x03[7:0] = 0x44		disable ELDR runction
l.	SYS_CLKR 0x08[15:0] = 0x3083		disable ELDR clock
m.	SYS_ISO_CTRL 0x01[7:0] = 0x83		isolated ELDR to PON
******************************/
	/* modify to 0x70a3 by Scott. */
1558
	rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
1559
	/* modify to 0x82 by Scott. */
1560
	rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
}

static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
{
	struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
	u16 value16 = 0;
	u8 value8 = 0;

	if (bWithoutHWSM) {
	/*****************************
	n.	LDOA15_CTRL 0x20[7:0] = 0x04	disable A15 power
	o.	LDOV12D_CTRL 0x21[7:0] = 0x54	disable digital core power
	r.	When driver call disable, the ASIC will turn off remaining
		clock automatically
	******************************/

1577
1578
		rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
		/* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
1579

1580
		value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
1581
		value8 &= (~LDV12_EN);
1582
		rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
/*		RT_TRACE(COMP_INIT, DBG_LOUD,
		(" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n", value8)); */
	}

	/*****************************
	h.	SPS0_CTRL 0x11[7:0] = 0x23		enter PFM mode
	i.	APS_FSMCO 0x04[15:0] = 0x4802		set USB suspend
	******************************/
	value8 = 0x23;
	if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1593
		value8 |= BIT(3);
1594

1595
	rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607

	if (bWithoutHWSM) {
		/* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
		/*  2010/08/31 According to Filen description, we need to
		    use HW to shut down 8051 automatically. */
		/*  Becasue suspend operatione need the asistance of 8051
		    to wait for 3ms. */
		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
	} else {
		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
	}

1608
	rtl8723au_write16(padapter, REG_APS_FSMCO, value16);	/* 0x4802 */
1609