macb.c 75.2 KB
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/*
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 * Cadence MACB/GEM Ethernet Controller driver
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 *
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/types.h>
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#include <linux/circ_buf.h>
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#include <linux/slab.h>
#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/dma-mapping.h>
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#include <linux/platform_data/macb.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include "macb.h"

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#define MACB_RX_BUFFER_SIZE	128
#define RX_BUFFER_MULTIPLE	64  /* bytes */
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#define RX_RING_SIZE		512 /* must be power of 2 */
#define RX_RING_BYTES		(sizeof(struct macb_dma_desc) * RX_RING_SIZE)
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#define TX_RING_SIZE		128 /* must be power of 2 */
#define TX_RING_BYTES		(sizeof(struct macb_dma_desc) * TX_RING_SIZE)
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/* level of occupied TX descriptors under which we wake up TX process */
#define MACB_TX_WAKEUP_THRESH	(3 * TX_RING_SIZE / 4)
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#define MACB_RX_INT_FLAGS	(MACB_BIT(RCOMP) | MACB_BIT(RXUBR)	\
				 | MACB_BIT(ISR_ROVR))
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#define MACB_TX_ERR_FLAGS	(MACB_BIT(ISR_TUND)			\
					| MACB_BIT(ISR_RLE)		\
					| MACB_BIT(TXERR))
#define MACB_TX_INT_FLAGS	(MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))

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#define MACB_MAX_TX_LEN		((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
#define GEM_MAX_TX_LEN		((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))

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#define GEM_MTU_MIN_SIZE	68

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/*
 * Graceful stop timeouts in us. We should allow up to
 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
 */
#define MACB_HALT_TIMEOUT	1230
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/* Ring buffer accessors */
static unsigned int macb_tx_ring_wrap(unsigned int index)
{
	return index & (TX_RING_SIZE - 1);
}

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static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
					  unsigned int index)
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{
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	return &queue->tx_ring[macb_tx_ring_wrap(index)];
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}

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static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
				       unsigned int index)
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{
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	return &queue->tx_skb[macb_tx_ring_wrap(index)];
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}

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static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
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{
	dma_addr_t offset;

	offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);

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	return queue->tx_ring_dma + offset;
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}

static unsigned int macb_rx_ring_wrap(unsigned int index)
{
	return index & (RX_RING_SIZE - 1);
}

static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
{
	return &bp->rx_ring[macb_rx_ring_wrap(index)];
}

static void *macb_rx_buffer(struct macb *bp, unsigned int index)
{
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	return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
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}

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/* I/O accessors */
static u32 hw_readl_native(struct macb *bp, int offset)
{
	return __raw_readl(bp->regs + offset);
}

static void hw_writel_native(struct macb *bp, int offset, u32 value)
{
	__raw_writel(value, bp->regs + offset);
}

static u32 hw_readl(struct macb *bp, int offset)
{
	return readl_relaxed(bp->regs + offset);
}

static void hw_writel(struct macb *bp, int offset, u32 value)
{
	writel_relaxed(value, bp->regs + offset);
}

/*
 * Find the CPU endianness by using the loopback bit of NCR register. When the
 * CPU is in big endian we need to program swaped mode for management
 * descriptor access.
 */
static bool hw_is_native_io(void __iomem *addr)
{
	u32 value = MACB_BIT(LLB);

	__raw_writel(value, addr + MACB_NCR);
	value = __raw_readl(addr + MACB_NCR);

	/* Write 0 back to disable everything */
	__raw_writel(0, addr + MACB_NCR);

	return value == MACB_BIT(LLB);
}

static bool hw_is_gem(void __iomem *addr, bool native_io)
{
	u32 id;

	if (native_io)
		id = __raw_readl(addr + MACB_MID);
	else
		id = readl_relaxed(addr + MACB_MID);

	return MACB_BFEXT(IDNUM, id) >= 0x2;
}

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static void macb_set_hwaddr(struct macb *bp)
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{
	u32 bottom;
	u16 top;

	bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
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	macb_or_gem_writel(bp, SA1B, bottom);
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	top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
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	macb_or_gem_writel(bp, SA1T, top);
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	/* Clear unused address register sets */
	macb_or_gem_writel(bp, SA2B, 0);
	macb_or_gem_writel(bp, SA2T, 0);
	macb_or_gem_writel(bp, SA3B, 0);
	macb_or_gem_writel(bp, SA3T, 0);
	macb_or_gem_writel(bp, SA4B, 0);
	macb_or_gem_writel(bp, SA4T, 0);
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}

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static void macb_get_hwaddr(struct macb *bp)
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{
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	struct macb_platform_data *pdata;
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	u32 bottom;
	u16 top;
	u8 addr[6];
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	int i;

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	pdata = dev_get_platdata(&bp->pdev->dev);
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	/* Check all 4 address register for vaild address */
	for (i = 0; i < 4; i++) {
		bottom = macb_or_gem_readl(bp, SA1B + i * 8);
		top = macb_or_gem_readl(bp, SA1T + i * 8);

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		if (pdata && pdata->rev_eth_addr) {
			addr[5] = bottom & 0xff;
			addr[4] = (bottom >> 8) & 0xff;
			addr[3] = (bottom >> 16) & 0xff;
			addr[2] = (bottom >> 24) & 0xff;
			addr[1] = top & 0xff;
			addr[0] = (top & 0xff00) >> 8;
		} else {
			addr[0] = bottom & 0xff;
			addr[1] = (bottom >> 8) & 0xff;
			addr[2] = (bottom >> 16) & 0xff;
			addr[3] = (bottom >> 24) & 0xff;
			addr[4] = top & 0xff;
			addr[5] = (top >> 8) & 0xff;
		}
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		if (is_valid_ether_addr(addr)) {
			memcpy(bp->dev->dev_addr, addr, sizeof(addr));
			return;
		}
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	}
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	dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
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	eth_hw_addr_random(bp->dev);
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}

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static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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	struct macb *bp = bus->priv;
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	int value;

	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
			      | MACB_BF(RW, MACB_MAN_READ)
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			      | MACB_BF(PHYA, mii_id)
			      | MACB_BF(REGA, regnum)
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			      | MACB_BF(CODE, MACB_MAN_CODE)));

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	/* wait for end of transfer */
	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
		cpu_relax();
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	value = MACB_BFEXT(DATA, macb_readl(bp, MAN));

	return value;
}

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static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
			   u16 value)
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{
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	struct macb *bp = bus->priv;
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	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
			      | MACB_BF(RW, MACB_MAN_WRITE)
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			      | MACB_BF(PHYA, mii_id)
			      | MACB_BF(REGA, regnum)
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			      | MACB_BF(CODE, MACB_MAN_CODE)
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			      | MACB_BF(DATA, value)));
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	/* wait for end of transfer */
	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
		cpu_relax();

	return 0;
}
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/**
 * macb_set_tx_clk() - Set a clock to a new frequency
 * @clk		Pointer to the clock to change
 * @rate	New frequency in Hz
 * @dev		Pointer to the struct net_device
 */
static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
{
	long ferr, rate, rate_rounded;

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	if (!clk)
		return;

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	switch (speed) {
	case SPEED_10:
		rate = 2500000;
		break;
	case SPEED_100:
		rate = 25000000;
		break;
	case SPEED_1000:
		rate = 125000000;
		break;
	default:
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		return;
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	}

	rate_rounded = clk_round_rate(clk, rate);
	if (rate_rounded < 0)
		return;

	/* RGMII allows 50 ppm frequency error. Test and warn if this limit
	 * is not satisfied.
	 */
	ferr = abs(rate_rounded - rate);
	ferr = DIV_ROUND_UP(ferr, rate / 100000);
	if (ferr > 5)
		netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
				rate);

	if (clk_set_rate(clk, rate_rounded))
		netdev_err(dev, "adjusting tx_clk failed.\n");
}

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static void macb_handle_link_change(struct net_device *dev)
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{
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	struct macb *bp = netdev_priv(dev);
	struct phy_device *phydev = bp->phy_dev;
	unsigned long flags;
	int status_change = 0;
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	spin_lock_irqsave(&bp->lock, flags);

	if (phydev->link) {
		if ((bp->speed != phydev->speed) ||
		    (bp->duplex != phydev->duplex)) {
			u32 reg;

			reg = macb_readl(bp, NCFGR);
			reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
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			if (macb_is_gem(bp))
				reg &= ~GEM_BIT(GBE);
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			if (phydev->duplex)
				reg |= MACB_BIT(FD);
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			if (phydev->speed == SPEED_100)
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				reg |= MACB_BIT(SPD);
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			if (phydev->speed == SPEED_1000 &&
			    bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
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				reg |= GEM_BIT(GBE);
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			macb_or_gem_writel(bp, NCFGR, reg);
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			bp->speed = phydev->speed;
			bp->duplex = phydev->duplex;
			status_change = 1;
		}
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	}

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	if (phydev->link != bp->link) {
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		if (!phydev->link) {
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			bp->speed = 0;
			bp->duplex = -1;
		}
		bp->link = phydev->link;
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		status_change = 1;
	}
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	spin_unlock_irqrestore(&bp->lock, flags);

	if (status_change) {
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		if (phydev->link) {
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			/* Update the TX clock rate if and only if the link is
			 * up and there has been a link change.
			 */
			macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);

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			netif_carrier_on(dev);
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			netdev_info(dev, "link up (%d/%s)\n",
				    phydev->speed,
				    phydev->duplex == DUPLEX_FULL ?
				    "Full" : "Half");
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		} else {
			netif_carrier_off(dev);
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			netdev_info(dev, "link down\n");
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		}
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	}
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}

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/* based on au1000_eth. c*/
static int macb_mii_probe(struct net_device *dev)
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{
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	struct macb *bp = netdev_priv(dev);
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	struct macb_platform_data *pdata;
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	struct phy_device *phydev;
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	int phy_irq;
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	int ret;
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	phydev = phy_find_first(bp->mii_bus);
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	if (!phydev) {
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		netdev_err(dev, "no PHY found\n");
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		return -ENXIO;
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	}

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	pdata = dev_get_platdata(&bp->pdev->dev);
	if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
		ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
		if (!ret) {
			phy_irq = gpio_to_irq(pdata->phy_irq_pin);
			phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
		}
	}
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	/* attach the mac to the phy */
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	ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
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				 bp->phy_interface);
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	if (ret) {
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		netdev_err(dev, "Could not attach to PHY\n");
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		return ret;
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	}

	/* mask with MAC supported features */
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	if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
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		phydev->supported &= PHY_GBIT_FEATURES;
	else
		phydev->supported &= PHY_BASIC_FEATURES;
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	if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
		phydev->supported &= ~SUPPORTED_1000baseT_Half;

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	phydev->advertising = phydev->supported;

	bp->link = 0;
	bp->speed = 0;
	bp->duplex = -1;
	bp->phy_dev = phydev;

	return 0;
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}

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static int macb_mii_init(struct macb *bp)
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{
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	struct macb_platform_data *pdata;
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	struct device_node *np;
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	int err = -ENXIO, i;
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	/* Enable management port */
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	macb_writel(bp, NCR, MACB_BIT(MPE));
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	bp->mii_bus = mdiobus_alloc();
	if (bp->mii_bus == NULL) {
		err = -ENOMEM;
		goto err_out;
	}

	bp->mii_bus->name = "MACB_mii_bus";
	bp->mii_bus->read = &macb_mdio_read;
	bp->mii_bus->write = &macb_mdio_write;
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	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
		bp->pdev->name, bp->pdev->id);
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	bp->mii_bus->priv = bp;
	bp->mii_bus->parent = &bp->dev->dev;
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	pdata = dev_get_platdata(&bp->pdev->dev);
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	dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
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	np = bp->pdev->dev.of_node;
	if (np) {
		/* try dt phy registration */
		err = of_mdiobus_register(bp->mii_bus, np);

		/* fallback to standard phy registration if no phy were
		   found during dt phy registration */
		if (!err && !phy_find_first(bp->mii_bus)) {
			for (i = 0; i < PHY_MAX_ADDR; i++) {
				struct phy_device *phydev;

				phydev = mdiobus_scan(bp->mii_bus, i);
				if (IS_ERR(phydev)) {
					err = PTR_ERR(phydev);
					break;
				}
			}

			if (err)
				goto err_out_unregister_bus;
		}
	} else {
		if (pdata)
			bp->mii_bus->phy_mask = pdata->phy_mask;

		err = mdiobus_register(bp->mii_bus);
	}

	if (err)
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		goto err_out_free_mdiobus;
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	err = macb_mii_probe(bp->dev);
	if (err)
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		goto err_out_unregister_bus;
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	return 0;
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err_out_unregister_bus:
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	mdiobus_unregister(bp->mii_bus);
err_out_free_mdiobus:
	mdiobus_free(bp->mii_bus);
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err_out:
	return err;
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}

static void macb_update_stats(struct macb *bp)
{
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	u32 *p = &bp->hw_stats.macb.rx_pause_frames;
	u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
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	int offset = MACB_PFR;
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	WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);

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	for(; p < end; p++, offset += 4)
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		*p += bp->macb_reg_readl(bp, offset);
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}

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static int macb_halt_tx(struct macb *bp)
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{
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	unsigned long	halt_time, timeout;
	u32		status;
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	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
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	timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
	do {
		halt_time = jiffies;
		status = macb_readl(bp, TSR);
		if (!(status & MACB_BIT(TGO)))
			return 0;
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		usleep_range(10, 250);
	} while (time_before(halt_time, timeout));
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	return -ETIMEDOUT;
}
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static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
{
	if (tx_skb->mapping) {
		if (tx_skb->mapped_as_page)
			dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
				       tx_skb->size, DMA_TO_DEVICE);
		else
			dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
					 tx_skb->size, DMA_TO_DEVICE);
		tx_skb->mapping = 0;
	}

	if (tx_skb->skb) {
		dev_kfree_skb_any(tx_skb->skb);
		tx_skb->skb = NULL;
	}
}

541
542
static void macb_tx_error_task(struct work_struct *work)
{
543
544
545
	struct macb_queue	*queue = container_of(work, struct macb_queue,
						      tx_error_task);
	struct macb		*bp = queue->bp;
546
	struct macb_tx_skb	*tx_skb;
547
	struct macb_dma_desc	*desc;
548
549
	struct sk_buff		*skb;
	unsigned int		tail;
550
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553
554
	unsigned long		flags;

	netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
		    (unsigned int)(queue - bp->queues),
		    queue->tx_tail, queue->tx_head);
555

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561
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	/* Prevent the queue IRQ handlers from running: each of them may call
	 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
	 * As explained below, we have to halt the transmission before updating
	 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
	 * network engine about the macb/gem being halted.
	 */
	spin_lock_irqsave(&bp->lock, flags);
563

564
	/* Make sure nobody is trying to queue up new packets */
565
	netif_tx_stop_all_queues(bp->dev);
566

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	/*
	 * Stop transmission now
	 * (in case we have just queued new packets)
570
	 * macb/gem must be halted to write TBQP register
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	 */
	if (macb_halt_tx(bp))
		/* Just complain for now, reinitializing TX path can be good */
		netdev_err(bp->dev, "BUG: halt tx timed out\n");
575

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579
	/*
	 * Treat frames in TX queue including the ones that caused the error.
	 * Free transmit buffers in upper layer.
	 */
580
581
	for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
		u32	ctrl;
582

583
		desc = macb_tx_desc(queue, tail);
584
		ctrl = desc->ctrl;
585
		tx_skb = macb_tx_skb(queue, tail);
586
		skb = tx_skb->skb;
587

588
		if (ctrl & MACB_BIT(TX_USED)) {
589
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591
592
			/* skb is set for the last buffer of the frame */
			while (!skb) {
				macb_tx_unmap(bp, tx_skb);
				tail++;
593
				tx_skb = macb_tx_skb(queue, tail);
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				skb = tx_skb->skb;
			}

			/* ctrl still refers to the first buffer descriptor
			 * since it's the only one written back by the hardware
			 */
			if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
				netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
					    macb_tx_ring_wrap(tail), skb->data);
				bp->stats.tx_packets++;
				bp->stats.tx_bytes += skb->len;
			}
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		} else {
			/*
			 * "Buffers exhausted mid-frame" errors may only happen
			 * if the driver is buggy, so complain loudly about those.
			 * Statistics are updated by hardware.
			 */
			if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
				netdev_err(bp->dev,
					   "BUG: TX buffers exhausted mid-frame\n");
615

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			desc->ctrl = ctrl | MACB_BIT(TX_USED);
		}

619
		macb_tx_unmap(bp, tx_skb);
620
621
	}

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	/* Set end of TX queue */
	desc = macb_tx_desc(queue, 0);
	desc->addr = 0;
	desc->ctrl = MACB_BIT(TX_USED);

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	/* Make descriptor updates visible to hardware */
	wmb();

	/* Reinitialize the TX desc queue */
631
	queue_writel(queue, TBQP, queue->tx_ring_dma);
632
	/* Make TX ring reflect state of hardware */
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	queue->tx_head = 0;
	queue->tx_tail = 0;
635
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637

	/* Housework before enabling TX IRQ */
	macb_writel(bp, TSR, macb_readl(bp, TSR));
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	queue_writel(queue, IER, MACB_TX_INT_FLAGS);

	/* Now we are ready to start transmission again */
	netif_tx_start_all_queues(bp->dev);
	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));

	spin_unlock_irqrestore(&bp->lock, flags);
645
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}

647
static void macb_tx_interrupt(struct macb_queue *queue)
648
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650
651
{
	unsigned int tail;
	unsigned int head;
	u32 status;
652
653
	struct macb *bp = queue->bp;
	u16 queue_index = queue - bp->queues;
654
655
656
657

	status = macb_readl(bp, TSR);
	macb_writel(bp, TSR, status);

658
	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
659
		queue_writel(queue, ISR, MACB_BIT(TCOMP));
660

661
662
	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
		(unsigned long)status);
663

664
665
	head = queue->tx_head;
	for (tail = queue->tx_tail; tail != head; tail++) {
666
667
668
669
		struct macb_tx_skb	*tx_skb;
		struct sk_buff		*skb;
		struct macb_dma_desc	*desc;
		u32			ctrl;
670

671
		desc = macb_tx_desc(queue, tail);
672

673
		/* Make hw descriptor updates visible to CPU */
674
		rmb();
675

676
		ctrl = desc->ctrl;
677

678
679
680
		/* TX_USED bit is only set by hardware on the very first buffer
		 * descriptor of the transmitted frame.
		 */
681
		if (!(ctrl & MACB_BIT(TX_USED)))
682
683
			break;

684
685
		/* Process all buffers of the current transmitted frame */
		for (;; tail++) {
686
			tx_skb = macb_tx_skb(queue, tail);
687
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			skb = tx_skb->skb;

			/* First, update TX stats if needed */
			if (skb) {
				netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
					    macb_tx_ring_wrap(tail), skb->data);
				bp->stats.tx_packets++;
				bp->stats.tx_bytes += skb->len;
			}
696

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			/* Now we can safely release resources */
			macb_tx_unmap(bp, tx_skb);

			/* skb is set only for the last buffer of the frame.
			 * WARNING: at this point skb has been freed by
			 * macb_tx_unmap().
			 */
			if (skb)
				break;
		}
707
708
	}

709
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	queue->tx_tail = tail;
	if (__netif_subqueue_stopped(bp->dev, queue_index) &&
	    CIRC_CNT(queue->tx_head, queue->tx_tail,
		     TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
		netif_wake_subqueue(bp->dev, queue_index);
714
715
}

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741
static void gem_rx_refill(struct macb *bp)
{
	unsigned int		entry;
	struct sk_buff		*skb;
	dma_addr_t		paddr;

	while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
		entry = macb_rx_ring_wrap(bp->rx_prepared_head);

		/* Make hw descriptor updates visible to CPU */
		rmb();

		bp->rx_prepared_head++;

		if (bp->rx_skbuff[entry] == NULL) {
			/* allocate sk_buff for this free entry in ring */
			skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
			if (unlikely(skb == NULL)) {
				netdev_err(bp->dev,
					   "Unable to allocate sk_buff\n");
				break;
			}

			/* now fill corresponding descriptor entry */
			paddr = dma_map_single(&bp->pdev->dev, skb->data,
					       bp->rx_buffer_size, DMA_FROM_DEVICE);
742
743
744
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746
747
			if (dma_mapping_error(&bp->pdev->dev, paddr)) {
				dev_kfree_skb(skb);
				break;
			}

			bp->rx_skbuff[entry] = skb;
748
749
750
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754
755

			if (entry == RX_RING_SIZE - 1)
				paddr |= MACB_BIT(RX_WRAP);
			bp->rx_ring[entry].addr = paddr;
			bp->rx_ring[entry].ctrl = 0;

			/* properly align Ethernet header */
			skb_reserve(skb, NET_IP_ALIGN);
756
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758
		} else {
			bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
			bp->rx_ring[entry].ctrl = 0;
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830
		}
	}

	/* Make descriptor updates visible to hardware */
	wmb();

	netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
		   bp->rx_prepared_head, bp->rx_tail);
}

/* Mark DMA descriptors from begin up to and not including end as unused */
static void discard_partial_frame(struct macb *bp, unsigned int begin,
				  unsigned int end)
{
	unsigned int frag;

	for (frag = begin; frag != end; frag++) {
		struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
		desc->addr &= ~MACB_BIT(RX_USED);
	}

	/* Make descriptor updates visible to hardware */
	wmb();

	/*
	 * When this happens, the hardware stats registers for
	 * whatever caused this is updated, so we don't have to record
	 * anything.
	 */
}

static int gem_rx(struct macb *bp, int budget)
{
	unsigned int		len;
	unsigned int		entry;
	struct sk_buff		*skb;
	struct macb_dma_desc	*desc;
	int			count = 0;

	while (count < budget) {
		u32 addr, ctrl;

		entry = macb_rx_ring_wrap(bp->rx_tail);
		desc = &bp->rx_ring[entry];

		/* Make hw descriptor updates visible to CPU */
		rmb();

		addr = desc->addr;
		ctrl = desc->ctrl;

		if (!(addr & MACB_BIT(RX_USED)))
			break;

		bp->rx_tail++;
		count++;

		if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
			netdev_err(bp->dev,
				   "not whole frame pointed by descriptor\n");
			bp->stats.rx_dropped++;
			break;
		}
		skb = bp->rx_skbuff[entry];
		if (unlikely(!skb)) {
			netdev_err(bp->dev,
				   "inconsistent Rx descriptor chain\n");
			bp->stats.rx_dropped++;
			break;
		}
		/* now everything is ready for receiving packet */
		bp->rx_skbuff[entry] = NULL;
831
		len = ctrl & bp->rx_frm_len_mask;
832
833
834
835
836
837

		netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);

		skb_put(skb, len);
		addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
		dma_unmap_single(&bp->pdev->dev, addr,
838
				 bp->rx_buffer_size, DMA_FROM_DEVICE);
839
840
841

		skb->protocol = eth_type_trans(skb, bp->dev);
		skb_checksum_none_assert(skb);
842
843
844
845
		if (bp->dev->features & NETIF_F_RXCSUM &&
		    !(bp->dev->flags & IFF_PROMISC) &&
		    GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
			skb->ip_summed = CHECKSUM_UNNECESSARY;
846
847
848
849
850
851
852
853

		bp->stats.rx_packets++;
		bp->stats.rx_bytes += skb->len;

#if defined(DEBUG) && defined(VERBOSE_DEBUG)
		netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
			    skb->len, skb->csum);
		print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
854
			       skb_mac_header(skb), 16, true);
855
856
857
858
859
860
861
862
863
864
865
866
		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
			       skb->data, 32, true);
#endif

		netif_receive_skb(skb);
	}

	gem_rx_refill(bp);

	return count;
}

867
868
869
870
871
static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
			 unsigned int last_frag)
{
	unsigned int len;
	unsigned int frag;
872
	unsigned int offset;
873
	struct sk_buff *skb;
874
	struct macb_dma_desc *desc;
875

876
	desc = macb_rx_desc(bp, last_frag);
877
	len = desc->ctrl & bp->rx_frm_len_mask;
878

879
	netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
880
881
		macb_rx_ring_wrap(first_frag),
		macb_rx_ring_wrap(last_frag), len);
882

883
884
885
886
887
888
889
890
891
892
	/*
	 * The ethernet header starts NET_IP_ALIGN bytes into the
	 * first buffer. Since the header is 14 bytes, this makes the
	 * payload word-aligned.
	 *
	 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
	 * the two padding bytes into the skb so that we avoid hitting
	 * the slowpath in memcpy(), and pull them off afterwards.
	 */
	skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
893
894
	if (!skb) {
		bp->stats.rx_dropped++;
895
896
897
		for (frag = first_frag; ; frag++) {
			desc = macb_rx_desc(bp, frag);
			desc->addr &= ~MACB_BIT(RX_USED);
898
899
900
			if (frag == last_frag)
				break;
		}
901
902

		/* Make descriptor updates visible to hardware */
903
		wmb();
904

905
906
907
		return 1;
	}

908
909
	offset = 0;
	len += NET_IP_ALIGN;
910
	skb_checksum_none_assert(skb);
911
912
	skb_put(skb, len);

913
	for (frag = first_frag; ; frag++) {
914
		unsigned int frag_len = bp->rx_buffer_size;
915
916
917
918
919

		if (offset + frag_len > len) {
			BUG_ON(frag != last_frag);
			frag_len = len - offset;
		}
920
		skb_copy_to_linear_data_offset(skb, offset,
921
				macb_rx_buffer(bp, frag), frag_len);
922
		offset += bp->rx_buffer_size;
923
924
		desc = macb_rx_desc(bp, frag);
		desc->addr &= ~MACB_BIT(RX_USED);
925
926
927
928
929

		if (frag == last_frag)
			break;
	}

930
931
932
	/* Make descriptor updates visible to hardware */
	wmb();

933
	__skb_pull(skb, NET_IP_ALIGN);
934
935
936
	skb->protocol = eth_type_trans(skb, bp->dev);

	bp->stats.rx_packets++;
937
	bp->stats.rx_bytes += skb->len;
938
	netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
939
		   skb->len, skb->csum);
940
941
942
943
944
945
946
947
	netif_receive_skb(skb);

	return 0;
}

static int macb_rx(struct macb *bp, int budget)
{
	int received = 0;
948
	unsigned int tail;
949
950
	int first_frag = -1;

951
952
	for (tail = bp->rx_tail; budget > 0; tail++) {
		struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
953
954
		u32 addr, ctrl;

955
		/* Make hw descriptor updates visible to CPU */
956
		rmb();
957

958
959
		addr = desc->addr;
		ctrl = desc->ctrl;
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990

		if (!(addr & MACB_BIT(RX_USED)))
			break;

		if (ctrl & MACB_BIT(RX_SOF)) {
			if (first_frag != -1)
				discard_partial_frame(bp, first_frag, tail);
			first_frag = tail;
		}

		if (ctrl & MACB_BIT(RX_EOF)) {
			int dropped;
			BUG_ON(first_frag == -1);

			dropped = macb_rx_frame(bp, first_frag, tail);
			first_frag = -1;
			if (!dropped) {
				received++;
				budget--;
			}
		}
	}

	if (first_frag != -1)
		bp->rx_tail = first_frag;
	else
		bp->rx_tail = tail;

	return received;
}

991
static int macb_poll(struct napi_struct *napi, int budget)
992
{
993
994
	struct macb *bp = container_of(napi, struct macb, napi);
	int work_done;
995
996
997
998
999
	u32 status;

	status = macb_readl(bp, RSR);
	macb_writel(bp, RSR, status);

1000
	work_done = 0;