intel_display.c 190 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dmi.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include "drmP.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "drm_dp_helper.h"
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#include "drm_crtc_helper.h"
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#include <linux/dma_remapping.h>
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#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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} intel_clock_t;

typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

#define INTEL_P2_NUM		      2
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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
	bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
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			int, int, intel_clock_t *, intel_clock_t *);
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock);
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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);
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static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
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		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock);
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static bool
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intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock);
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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_display_port = {
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	.dot = { .min = 161670, .max = 227000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 97, .max = 108 },
	.m1 = { .min = 0x10, .max = 0x12 },
	.m2 = { .min = 0x05, .max = 0x06 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_g4x_dp,
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_find_best_PLL,
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 81, .max = 90 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_ironlake_dp,
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};

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u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
	unsigned long flags;
	u32 val = 0;

	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO idle wait timed out\n");
		goto out_unlock;
	}

	I915_WRITE(DPIO_REG, reg);
	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
		   DPIO_BYTE);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO read wait timed out\n");
		goto out_unlock;
	}
	val = I915_READ(DPIO_DATA);

out_unlock:
	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
	return val;
}

static void vlv_init_dpio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Reset the DPIO config */
	I915_WRITE(DPIO_CTL, 0);
	POSTING_READ(DPIO_CTL);
	I915_WRITE(DPIO_CTL, 1);
	POSTING_READ(DPIO_CTL);
}

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static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
{
	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
	return 1;
}

static const struct dmi_system_id intel_dual_link_lvds[] = {
	{
		.callback = intel_dual_link_lvds_callback,
		.ident = "Apple MacBook Pro (Core i5/i7 Series)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
		},
	},
	{ }	/* terminating entry */
};

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static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
			      unsigned int reg)
{
	unsigned int val;

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	/* use the module option value if specified */
	if (i915_lvds_channel_mode > 0)
		return i915_lvds_channel_mode == 2;

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	if (dmi_check_system(intel_dual_link_lvds))
		return true;

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	if (dev_priv->lvds_val)
		val = dev_priv->lvds_val;
	else {
		/* BIOS should set the proper LVDS register value at boot, but
		 * in reality, it doesn't set the value when the lid is closed;
		 * we need to check "the value to be set" in VBT when LVDS
		 * register is uninitialized.
		 */
		val = I915_READ(reg);
		if (!(val & ~LVDS_DETECTED))
			val = dev_priv->bios_lvds_val;
		dev_priv->lvds_val = val;
	}
	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
}

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
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			/* LVDS dual channel */
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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			HAS_eDP)
		limit = &intel_limits_ironlake_display_port;
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	else
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		limit = &intel_limits_ironlake_dac;
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	return limit;
}

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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (is_dual_link_lvds(dev_priv, LVDS))
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			/* LVDS with dual channel */
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			limit = &intel_limits_g4x_dual_channel_lvds;
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		else
			/* LVDS with dual channel */
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			limit = &intel_limits_g4x_single_channel_lvds;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
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		limit = &intel_limits_g4x_hdmi;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
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		limit = &intel_limits_g4x_sdvo;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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		limit = &intel_limits_g4x_display_port;
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	} else /* The option is for other outputs */
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		limit = &intel_limits_i9xx_sdvo;
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	return limit;
}

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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

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	if (HAS_PCH_SPLIT(dev))
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		limit = intel_ironlake_limit(crtc, refclk);
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	else if (IS_G4X(dev)) {
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		limit = intel_g4x_limit(crtc);
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	} else if (IS_PINEVIEW(dev)) {
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		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_pineview_lvds;
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		else
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			limit = &intel_limits_pineview_sdvo;
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	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
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	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_i8xx_lvds;
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		else
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			limit = &intel_limits_i8xx_dvo;
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	}
	return limit;
}

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/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
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{
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	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
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	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
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		return;
	}
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	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->base.crtc == crtc && encoder->type == type)
			return true;

	return false;
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}

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#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

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static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
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{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
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		INTELPllInvalid("p1 out of range\n");
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	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
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		INTELPllInvalid("p out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
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		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
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		INTELPllInvalid("m1 out of range\n");
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	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
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		INTELPllInvalid("m1 <= m2\n");
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	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
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		INTELPllInvalid("m out of range\n");
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	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
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		INTELPllInvalid("n out of range\n");
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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
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		INTELPllInvalid("dot out of range\n");
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	return true;
}

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int err = target;

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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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	    (I915_READ(LVDS)) != 0) {
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		/*
		 * For LVDS, if the panel is on, just rely on its current
		 * settings for dual-channel.  We haven't figured out how to
		 * reliably set up different single/dual channel state, if we
		 * even can.
		 */
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		if (is_dual_link_lvds(dev_priv, LVDS))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

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	memset(best_clock, 0, sizeof(*best_clock));
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	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
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			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
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				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

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					intel_clock(dev, refclk, &clock);
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					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
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					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int max_n;
	bool found;
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	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
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	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		int lvds_reg;

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		if (HAS_PCH_SPLIT(dev))
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			lvds_reg = PCH_LVDS;
		else
			lvds_reg = LVDS;
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
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		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
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	/* based on hardware requirement, prefer smaller n to precision */
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	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
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		/* based on hardware requirement, prefere larger m1,m2 */
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		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

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					intel_clock(dev, refclk, &clock);
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					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
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					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
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					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
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	return found;
}

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intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
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			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
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	if (target < 200000) {
		clock.n = 1;
		clock.p1 = 2;
		clock.p2 = 10;
		clock.m1 = 12;
		clock.m2 = 9;
	} else {
		clock.n = 2;
		clock.p1 = 1;
		clock.p2 = 10;
		clock.m1 = 14;
		clock.m2 = 8;
	}
	intel_clock(dev, refclk, &clock);
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

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/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
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		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock)
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{
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	intel_clock_t clock;
	if (target < 200000) {
		clock.p1 = 2;
		clock.p2 = 10;
		clock.n = 2;
		clock.m1 = 23;
		clock.m2 = 8;
	} else {
		clock.p1 = 1;
		clock.p2 = 10;
		clock.n = 1;
		clock.m1 = 14;
		clock.m2 = 2;
	}
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
	clock.p = (clock.p1 * clock.p2);
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
	clock.vco = 0;
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
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}

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static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 frame, frame_reg = PIPEFRAME(pipe);

	frame = I915_READ(frame_reg);

	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

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/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	int pipestat_reg = PIPESTAT(pipe);
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	if (INTEL_INFO(dev)->gen >= 5) {
		ironlake_wait_for_vblank(dev, pipe);
		return;
	}

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	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

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	/* Wait for vblank interrupt bit to set */
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	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
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		DRM_DEBUG_KMS("vblank wait timed out\n");
}

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/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
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 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
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 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
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 *
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 */
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void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (INTEL_INFO(dev)->gen >= 4) {
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		int reg = PIPECONF(pipe);
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		/* Wait for the Pipe State to go off */
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		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
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			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	} else {
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		u32 last_line, line_mask;
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		int reg = PIPEDSL(pipe);
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		unsigned long timeout = jiffies + msecs_to_jiffies(100);

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		if (IS_GEN2(dev))
			line_mask = DSL_LINEMASK_GEN2;
		else
			line_mask = DSL_LINEMASK_GEN3;

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		/* Wait for the display line to settle */
		do {
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			last_line = I915_READ(reg) & line_mask;
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			mdelay(5);
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		} while (((I915_READ(reg) & line_mask) != last_line) &&
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			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	}
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}

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static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

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/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
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			   struct intel_pch_pll *pll,
			   struct intel_crtc *crtc,
			   bool state)
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{
	u32 val;
	bool cur_state;

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	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		return;
	}

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	if (WARN (!pll,
		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
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		return;

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	val = I915_READ(pll->pll_reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
	     pll->pll_reg, state_string(state), state_string(cur_state), val);

	/* Make sure the selected PLL is correctly attached to the transcoder */
	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
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		u32 pch_dpll;

		pch_dpll = I915_READ(PCH_DPLL_SEL);
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		cur_state = pll->pll_reg == _PCH_DPLL_B;
		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
			  "PLL[%d] not attached to this transcoder %d: %08x\n",
			  cur_state, crtc->pipe, pch_dpll)) {
			cur_state = !!(val >> (4*crtc->pipe + 3));
			WARN(cur_state != state,
			     "PLL[%d] not %s on this transcoder %d: %08x\n",
			     pll->pll_reg == _PCH_DPLL_B,
			     state_string(state),
			     crtc->pipe,
			     val);
		}
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	}
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}
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#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
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static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

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	if (IS_HASWELL(dev_priv->dev)) {
		/* On Haswell, DDI is used instead of FDI_TX_CTL */
		reg = DDI_FUNC_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
	} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
	}
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	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

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	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
			return;
	} else {
		reg = FDI_RX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_RX_ENABLE);
	}
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	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

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	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
	if (IS_HASWELL(dev_priv->dev))
		return;

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	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

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	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
		return;
	}
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	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

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static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
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	bool locked = true;
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	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
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	     pipe_name(pipe));
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}

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void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
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{
	int reg;
	u32 val;
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	bool cur_state;
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	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

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	reg = PIPECONF(pipe);
	val = I915_READ(reg);
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	cur_state = !!(val & PIPECONF_ENABLE);
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
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	     pipe_name(pipe), state_string(state), state_string(cur_state));
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}

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static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
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{
	int reg;
	u32 val;
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	bool cur_state;
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	reg = DSPCNTR(plane);
	val = I915_READ(reg);
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	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
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}

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#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

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static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
	int reg, i;
	u32 val;
	int cur_pipe;

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	/* Planes are fixed to pipes on ILK+ */
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	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
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		return;
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	}
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	/* Need to check both planes against the pipe */
	for (i = 0; i < 2; i++) {
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
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		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
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	}
}

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static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

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	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		return;
	}

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	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
				       enum pipe pipe)
{
	int reg;
	u32 val;
	bool enabled;

	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
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	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
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}

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static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
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{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

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static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & PORT_ENABLE) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if