i7core_edac.c 63.6 KB
Newer Older
1 2
/* Intel i7 core/Nehalem Memory Controller kernel module
 *
3
 * This driver supports the memory controllers found on the Intel
4 5 6
 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
 * and Westmere-EP.
7 8 9 10
 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
11
 * Copyright (c) 2009-2010 by:
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
Randy Dunlap's avatar
Randy Dunlap committed
33
#include <linux/delay.h>
Nils Carlson's avatar
Nils Carlson committed
34
#include <linux/dmi.h>
35 36
#include <linux/edac.h>
#include <linux/mmzone.h>
37
#include <linux/smp.h>
38
#include <asm/mce.h>
39
#include <asm/processor.h>
40
#include <asm/div64.h>
41 42 43

#include "edac_core.h"

44 45 46 47 48
/* Static vars */
static LIST_HEAD(i7core_edac_list);
static DEFINE_MUTEX(i7core_edac_lock);
static int probed;

49 50 51
static int use_pci_fixup;
module_param(use_pci_fixup, int, 0444);
MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
52 53 54 55 56 57 58 59 60
/*
 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
 * registers start at bus 255, and are not reported by BIOS.
 * We currently find devices with only 2 sockets. In order to support more QPI
 * Quick Path Interconnect, just increment this number.
 */
#define MAX_SOCKET_BUSES	2


61 62 63
/*
 * Alter this version for the module when modifications are made
 */
Michal Marek's avatar
Michal Marek committed
64
#define I7CORE_REVISION    " Ver: 1.0.0"
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
#define EDAC_MOD_STR      "i7core_edac"

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

80 81 82
	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90
83 84
  #define MC_CFG_UNLOCK		0x02
  #define MC_CFG_LOCK		0x00
85

86 87 88 89 90 91
	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

92 93 94 95 96 97 98 99 100 101 102 103
/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

104
/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
105 106 107 108 109 110 111
#define MC_SSRCONTROL		0x48
  #define SSR_MODE_DISABLE	0x00
  #define SSR_MODE_ENABLE	0x01
  #define SSR_MODE_MASK		0x03

#define MC_SCRUB_CONTROL	0x4c
  #define STARTSCRUB		(1 << 24)
Nils Carlson's avatar
Nils Carlson committed
112
  #define SCRUBINTERVAL_MASK    0xffffff
113

114 115 116 117 118 119 120 121 122 123 124
#define MC_COR_ECC_CNT_0	0x80
#define MC_COR_ECC_CNT_1	0x84
#define MC_COR_ECC_CNT_2	0x88
#define MC_COR_ECC_CNT_3	0x8c
#define MC_COR_ECC_CNT_4	0x90
#define MC_COR_ECC_CNT_5	0x94

#define DIMM_TOP_COR_ERR(r)			(((r) >> 16) & 0x7fff)
#define DIMM_BOT_COR_ERR(r)			((r) & 0x7fff)


125 126
	/* OFFSETS for Devices 4,5 and 6 Function 0 */

127 128 129 130 131 132
#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

133 134 135 136
#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

137 138 139
#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

140
#define MC_CHANNEL_ADDR_MATCH	0xf0
141 142 143 144 145 146 147 148 149 150
#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
151

152
	/* OFFSETS for Devices 4,5 and 6 Function 1 */
153

154 155 156 157 158 159 160
#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
161 162 163 164
  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
165
  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
166
  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
167 168
  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
169

170 171
#define MC_RANK_PRESENT		0x7c

172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194
#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

195 196 197 198 199
/*
 * i7core structs
 */

#define NUM_CHANS 3
200 201 202
#define MAX_DIMMS 3		/* Max DIMMS per channel */
#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
203 204 205 206 207

struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
208
	u32	ch_map;
209 210
};

211 212 213 214 215 216 217 218 219 220 221 222

struct i7core_inject {
	int	enable;

	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

223
struct i7core_channel {
224 225 226
	bool		is_3dimms_present;
	bool		is_single_4rank;
	bool		has_4rank;
227
	u32		dimms;
228 229
};

230
struct pci_id_descr {
231 232 233
	int			dev;
	int			func;
	int 			dev_id;
234
	int			optional;
235 236
};

237
struct pci_id_table {
238 239
	const struct pci_id_descr	*descr;
	int				n_devs;
240 241
};

242 243 244 245
struct i7core_dev {
	struct list_head	list;
	u8			socket;
	struct pci_dev		**pdev;
246
	int			n_devs;
247 248 249
	struct mem_ctl_info	*mci;
};

250
struct i7core_pvt {
251 252
	struct device addrmatch_dev, chancounts_dev;

253 254 255 256 257
	struct pci_dev	*pci_noncore;
	struct pci_dev	*pci_mcr[MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];

	struct i7core_dev *i7core_dev;
258

259
	struct i7core_info	info;
260
	struct i7core_inject	inject;
261
	struct i7core_channel	channel[NUM_CHANS];
262

263
	int		ce_count_available;
264 265

			/* ECC corrected errors counts per udimm */
266 267
	unsigned long	udimm_ce_count[MAX_DIMMS];
	int		udimm_last_ce_count[MAX_DIMMS];
268
			/* ECC corrected errors counts per rdimm */
269 270
	unsigned long	rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
	int		rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
271

272
	bool		is_registered, enable_scrub;
273

274
	/* Fifo double buffers */
275
	struct mce		mce_entry[MCE_LOG_LEN];
276 277 278 279 280 281 282
	struct mce		mce_outentry[MCE_LOG_LEN];

	/* Fifo in/out counters */
	unsigned		mce_in, mce_out;

	/* Count indicator to show errors not got */
	unsigned		mce_overrun;
283

Nils Carlson's avatar
Nils Carlson committed
284 285 286
	/* DCLK Frequency used for computing scrub rate */
	int			dclk_freq;

287 288
	/* Struct to control EDAC polling */
	struct edac_pci_ctl_info *i7core_pci;
289 290
};

291 292 293 294 295
#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

296
static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
297 298 299
		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
300
			/* Exists only for RDIMM */
301
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
321 322 323 324 325 326 327 328 329 330

		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },

331
};
332

333
static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
334 335 336 337 338 339 340 341 342
	{ PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
	{ PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
	{ PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },

	{ PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
	{ PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
	{ PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
	{ PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC)   },

343 344 345 346
	{ PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
	{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
	{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
	{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
347 348 349 350 351 352

	/*
	 * This is the PCI device has an alternate address on some
	 * processors like Core i7 860
	 */
	{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
353 354
};

355
static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379
		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1  },
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },
380 381 382 383

		/* Generic Non-core registers */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },

384 385
};

386 387
#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
static const struct pci_id_table pci_dev_table[] = {
388 389 390
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
391
	{0,}			/* 0 terminated list. */
392 393
};

394 395 396
/*
 *	pci_device_id	table for which devices we are looking for
 */
397
static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
398
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
399
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
400 401 402
	{0,}			/* 0 terminated list. */
};

403 404 405 406 407
/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
408 409
#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
410 411

	/* MC_STATUS bits */
412
#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
413
#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
414 415

	/* MC_MAX_DOD read functions */
416
static inline int numdimms(u32 dimms)
417
{
418
	return (dimms & 0x3) + 1;
419 420
}

421
static inline int numrank(u32 rank)
422 423 424
{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

425
	return ranks[rank & 0x3];
426 427
}

428
static inline int numbank(u32 bank)
429 430 431
{
	static int banks[4] = { 4, 8, 16, -EINVAL };

432
	return banks[bank & 0x3];
433 434
}

435
static inline int numrow(u32 row)
436 437 438 439 440 441
{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

442
	return rows[row & 0x7];
443 444
}

445
static inline int numcol(u32 col)
446 447 448 449
{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
450
	return cols[col & 0x3];
451 452
}

453
static struct i7core_dev *get_i7core_dev(u8 socket)
454 455 456 457 458 459 460 461 462 463 464
{
	struct i7core_dev *i7core_dev;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
		if (i7core_dev->socket == socket)
			return i7core_dev;
	}

	return NULL;
}

465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487
static struct i7core_dev *alloc_i7core_dev(u8 socket,
					   const struct pci_id_table *table)
{
	struct i7core_dev *i7core_dev;

	i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
	if (!i7core_dev)
		return NULL;

	i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
				   GFP_KERNEL);
	if (!i7core_dev->pdev) {
		kfree(i7core_dev);
		return NULL;
	}

	i7core_dev->socket = socket;
	i7core_dev->n_devs = table->n_devs;
	list_add_tail(&i7core_dev->list, &i7core_edac_list);

	return i7core_dev;
}

488 489 490 491 492 493 494
static void free_i7core_dev(struct i7core_dev *i7core_dev)
{
	list_del(&i7core_dev->list);
	kfree(i7core_dev->pdev);
	kfree(i7core_dev);
}

495 496 497
/****************************************************************************
			Memory check routines
 ****************************************************************************/
498

499
static int get_dimm_config(struct mem_ctl_info *mci)
500 501
{
	struct i7core_pvt *pvt = mci->pvt_info;
502
	struct pci_dev *pdev;
503
	int i, j;
504
	enum edac_type mode;
505
	enum mem_type mtype;
506
	struct dimm_info *dimm;
507

508
	/* Get data from the MC register, function 0 */
509
	pdev = pvt->pci_mcr[0];
510
	if (!pdev)
511 512
		return -ENODEV;

513
	/* Device 3 function 0 reads */
514 515 516 517
	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
518

519
	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
520
		pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
521
		pvt->info.max_dod, pvt->info.ch_map);
522

523
	if (ECC_ENABLED(pvt)) {
524
		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
525 526 527 528 529
		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
530
		debugf0("ECC disabled\n");
531 532
		mode = EDAC_NONE;
	}
533 534

	/* FIXME: need to handle the error codes */
535 536
	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
537 538
		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
539
		numbank(pvt->info.max_dod >> 4),
540 541
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
542

543
	for (i = 0; i < NUM_CHANS; i++) {
544
		u32 data, dimm_dod[3], value[8];
545

546 547 548
		if (!pvt->pci_ch[i][0])
			continue;

549 550 551 552 553 554 555 556 557
		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

558
		/* Devices 4-6 function 0 */
559
		pci_read_config_dword(pvt->pci_ch[i][0],
560 561
				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

562 563 564 565 566 567 568 569 570

		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].is_3dimms_present = true;

		if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].is_single_4rank = true;

		if (data & QUAD_RANK_PRESENT)
			pvt->channel[i].has_4rank = true;
571

572 573
		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
574
		else
575 576 577
			mtype = MEM_DDR3;

		/* Devices 4-6 function 1 */
578
		pci_read_config_dword(pvt->pci_ch[i][1],
579
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
580
		pci_read_config_dword(pvt->pci_ch[i][1],
581
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
582
		pci_read_config_dword(pvt->pci_ch[i][1],
583
				MC_DOD_CH_DIMM2, &dimm_dod[2]);
584

585
		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
586
			"%s%s%s%cDIMMs\n",
587 588 589
			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
590 591 592
			pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
			pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
			pvt->channel[i].has_4rank ? "HAS_4R " : "",
593
			(data & REGISTERED_DIMM) ? 'R' : 'U');
594 595 596

		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
597
			u32 size, npages;
598 599 600 601

			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

602 603
			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
				       i, j, 0);
604 605 606 607 608
			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

609 610 611
			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

612 613 614
			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
615 616 617
				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

618
			npages = MiB_TO_PAGES(size);
619

620 621
			dimm->nr_pages = npages;

622 623
			switch (banks) {
			case 4:
624
				dimm->dtype = DEV_X4;
625 626
				break;
			case 8:
627
				dimm->dtype = DEV_X8;
628 629
				break;
			case 16:
630
				dimm->dtype = DEV_X16;
631 632
				break;
			default:
633
				dimm->dtype = DEV_UNKNOWN;
634 635
			}

636 637 638 639 640 641
			snprintf(dimm->label, sizeof(dimm->label),
				 "CPU#%uChannel#%u_DIMM#%u",
				 pvt->i7core_dev->socket, i, j);
			dimm->grain = 8;
			dimm->edac_mode = mode;
			dimm->mtype = mtype;
642
		}
643

644 645 646 647 648 649 650 651
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
652
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
653
		for (j = 0; j < 8; j++)
654
			debugf1("\t\t%#x\t%#x\t%#x\n",
655 656
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
657
				(value[j] & ((1 << 24) - 1)));
658 659
	}

660 661 662
	return 0;
}

663 664 665 666
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

667 668
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

669 670 671 672 673 674 675
/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
676
static int disable_inject(const struct mem_ctl_info *mci)
677 678 679 680 681
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

682
	if (!pvt->pci_ch[pvt->inject.channel][0])
683 684
		return -ENODEV;

685
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
686
				MC_CHANNEL_ERROR_INJECT, 0);
687 688

	return 0;
689 690 691 692 693 694 695 696 697
}

/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
698 699
static ssize_t i7core_inject_section_store(struct device *dev,
					   struct device_attribute *mattr,
700 701
					   const char *data, size_t count)
{
702
	struct mem_ctl_info *mci = to_mci(dev);
703 704 705 706 707
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
708
		disable_inject(mci);
709 710 711

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
712
		return -EIO;
713 714 715 716 717

	pvt->inject.section = (u32) value;
	return count;
}

718 719 720
static ssize_t i7core_inject_section_show(struct device *dev,
					  struct device_attribute *mattr,
					  char *data)
721
{
722
	struct mem_ctl_info *mci = to_mci(dev);
723 724 725 726 727 728 729 730 731 732 733 734
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
735 736
static ssize_t i7core_inject_type_store(struct device *dev,
					struct device_attribute *mattr,
737 738
					const char *data, size_t count)
{
739 740
	struct mem_ctl_info *mci = to_mci(dev);
struct i7core_pvt *pvt = mci->pvt_info;
741 742 743 744
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
745
		disable_inject(mci);
746 747 748

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
749
		return -EIO;
750 751 752 753 754

	pvt->inject.type = (u32) value;
	return count;
}

755 756 757
static ssize_t i7core_inject_type_show(struct device *dev,
				       struct device_attribute *mattr,
				       char *data)
758
{
759
	struct mem_ctl_info *mci = to_mci(dev);
760
	struct i7core_pvt *pvt = mci->pvt_info;
761

762 763 764 765 766 767 768 769 770 771 772 773 774
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
775 776 777
static ssize_t i7core_inject_eccmask_store(struct device *dev,
					   struct device_attribute *mattr,
					   const char *data, size_t count)
778
{
779
	struct mem_ctl_info *mci = to_mci(dev);
780 781 782 783 784
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
785
		disable_inject(mci);
786 787 788

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
789
		return -EIO;
790 791 792 793 794

	pvt->inject.eccmask = (u32) value;
	return count;
}

795 796 797
static ssize_t i7core_inject_eccmask_show(struct device *dev,
					  struct device_attribute *mattr,
					  char *data)
798
{
799
	struct mem_ctl_info *mci = to_mci(dev);
800
	struct i7core_pvt *pvt = mci->pvt_info;
801

802 803 804 805 806 807 808 809 810 811 812 813 814 815
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */

816 817
#define DECLARE_ADDR_MATCH(param, limit)			\
static ssize_t i7core_inject_store_##param(			\
818 819 820
	struct device *dev,					\
	struct device_attribute *mattr,				\
	const char *data, size_t count)				\
821
{								\
822
	struct mem_ctl_info *mci = to_mci(dev);			\
823
	struct i7core_pvt *pvt;					\
824 825 826
	long value;						\
	int rc;							\
								\
827 828 829
	debugf1("%s()\n", __func__);				\
	pvt = mci->pvt_info;					\
								\
830 831 832
	if (pvt->inject.enable)					\
		disable_inject(mci);				\
								\
833
	if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
834 835 836 837 838 839 840 841 842 843 844 845 846
		value = -1;					\
	else {							\
		rc = strict_strtoul(data, 10, &value);		\
		if ((rc < 0) || (value >= limit))		\
			return -EIO;				\
	}							\
								\
	pvt->inject.param = value;				\
								\
	return count;						\
}								\
								\
static ssize_t i7core_inject_show_##param(			\
847 848 849
	struct device *dev,					\
	struct device_attribute *mattr,				\
	char *data)						\
850
{								\
851
	struct mem_ctl_info *mci = to_mci(dev);			\
852 853 854 855
	struct i7core_pvt *pvt;					\
								\
	pvt = mci->pvt_info;					\
	debugf1("%s() pvt=%p\n", __func__, pvt);		\
856 857 858 859
	if (pvt->inject.param < 0)				\
		return sprintf(data, "any\n");			\
	else							\
		return sprintf(data, "%d\n", pvt->inject.param);\
860 861
}

862
#define ATTR_ADDR_MATCH(param)					\
863 864 865
	static DEVICE_ATTR(param, S_IRUGO | S_IWUSR,		\
		    i7core_inject_show_##param,			\
		    i7core_inject_store_##param)
866

867 868 869 870 871 872
DECLARE_ADDR_MATCH(channel, 3);
DECLARE_ADDR_MATCH(dimm, 3);
DECLARE_ADDR_MATCH(rank, 4);
DECLARE_ADDR_MATCH(bank, 32);
DECLARE_ADDR_MATCH(page, 0x10000);
DECLARE_ADDR_MATCH(col, 0x4000);
873

874 875 876 877 878 879 880
ATTR_ADDR_MATCH(channel);
ATTR_ADDR_MATCH(dimm);
ATTR_ADDR_MATCH(rank);
ATTR_ADDR_MATCH(bank);
ATTR_ADDR_MATCH(page);
ATTR_ADDR_MATCH(col);

881
static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
882 883 884 885
{
	u32 read;
	int count;

886 887 888 889
	debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val);

890 891
	for (count = 0; count < 10; count++) {
		if (count)
892
			msleep(100);
893 894 895 896 897 898 899
		pci_write_config_dword(dev, where, val);
		pci_read_config_dword(dev, where, &read);

		if (read == val)
			return 0;
	}

900 901 902 903
	i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
		"write=%08x. Read=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val, read);
904 905 906 907

	return -EINVAL;
}

908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925
/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
926 927 928
static ssize_t i7core_inject_enable_store(struct device *dev,
					  struct device_attribute *mattr,
					  const char *data, size_t count)
929
{
930
	struct mem_ctl_info *mci = to_mci(dev);
931 932 933 934 935 936
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

937
	if (!pvt->pci_ch[pvt->inject.channel][0])
938 939
		return 0;

940 941 942 943 944 945 946 947 948 949 950 951 952
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
953
		mask |= 1LL << 41;
954
	else {
955
		if (pvt->channel[pvt->inject.channel].dimms > 2)
956
			mask |= (pvt->inject.dimm & 0x3LL) << 35;
957
		else
958
			mask |= (pvt->inject.dimm & 0x1LL) << 36;
959 960 961 962
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
963
		mask |= 1LL << 40;
964
	else {
965
		if (pvt->channel[pvt->inject.channel].dimms > 2)
966
			mask |= (pvt->inject.rank & 0x1LL) << 34;
967
		else
968
			mask |= (pvt->inject.rank & 0x3LL) << 34;
969 970 971 972
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
973
		mask |= 1LL << 39;
974
	else
975
		mask |= (pvt->inject.bank & 0x15LL) << 30;
976 977 978

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
979
		mask |= 1LL << 38;
980
	else
981
		mask |= (pvt->inject.page & 0xffff) << 14;
982 983 984

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
985
		mask |= 1LL << 37;
986
	else
987
		mask |= (pvt->inject.col & 0x3fff);
988

989 990 991 992 993 994 995 996 997 998 999 1000
	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
		     (pvt->inject.type & 0x6) << (3 - 1);

	/* Unlock writes to registers - this register is write only */
1001
	pci_write_config_dword(pvt->pci_noncore,
1002
			       MC_CFG_CONTROL, 0x2);
1003

1004
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1005
			       MC_CHANNEL_ADDR_MATCH, mask);
1006
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1007 1008
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);

1009
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1010 1011
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

1012
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1013
			       MC_CHANNEL_ERROR_INJECT, injectmask);
1014

1015
	/*
1016 1017 1018
	 * This is something undocumented, based on my tests
	 * Without writing 8 to this register, errors aren't injected. Not sure
	 * why.
1019
	 */
1020
	pci_write_config_dword(pvt->pci_noncore,
1021
			       MC_CFG_CONTROL, 8);
1022

1023 1024
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
1025 1026
		mask, pvt->inject.eccmask, injectmask);

1027

1028 1029 1030
	return count;
}

1031 1032 1033
static ssize_t i7core_inject_enable_show(struct device *dev,
					 struct device_attribute *mattr,
					 char *data)
1034
{
1035
	struct mem_ctl_info *mci = to_mci(dev);
1036
	struct i7core_pvt *pvt = mci->pvt_info;
1037 1038
	u32 injectmask;

1039 1040 1041
	if (!pvt->pci_ch[pvt->inject.channel][0])
		return 0;

1042
	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1043
			       MC_CHANNEL_ERROR_INJECT, &injectmask);
1044 1045 1046 1047 1048 1049

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1050 1051 1052
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1053 1054
#define DECLARE_COUNTER(param)					\
static ssize_t i7core_show_counter_##param(			\
1055 1056 1057
	struct device *dev,					\
	struct device_attribute *mattr,				\
	char *data)						\
1058
{								\
1059
	struct mem_ctl_info *mci = to_mci(dev);			\
1060 1061
	struct i7core_pvt *pvt = mci->pvt_info;			\
								\
1062
	debugf1("%s()\n", __func__);				\
1063 1064 1065 1066 1067
	if (!pvt->ce_count_available || (pvt->is_registered))	\
		return sprintf(data, "data unavailable\n");	\
	return sprintf(data, "%lu\n",				\
			pvt->udimm_ce_count[param]);		\
}
1068

1069
#define ATTR_COUNTER(param)					\
1070 1071 1072
	static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR,	\
		    i7core_show_counter_##param,		\
		    NULL)
1073

1074 1075 1076
DECLARE_COUNTER(0);
DECLARE_COUNTER(1);
DECLARE_COUNTER(2);
1077

1078 1079 1080 1081
ATTR_COUNTER(0);
ATTR_COUNTER(1);
ATTR_COUNTER(2);

1082
/*
1083
 * inject_addrmatch device sysfs struct
1084
 */
1085

1086 1087 1088 1089 1090 1091 1092 1093
static struct attribute *i7core_addrmatch_attrs[] = {
	&dev_attr_channel.attr,
	&dev_attr_dimm.attr,
	&dev_attr_rank.attr,
	&dev_attr_bank.attr,
	&dev_attr_page.attr,
	&dev_attr_col.attr,
	NULL
1094 1095
};

1096 1097
static struct attribute_group addrmatch_grp = {
	.attrs	= i7core_addrmatch_attrs,
1098 1099
};

1100 1101 1102
static const struct attribute_group *addrmatch_groups[] = {
	&addrmatch_grp,
	NULL
1103 1104
};

1105 1106 1107 1108 1109 1110 1111 1112
static void addrmatch_release(struct device *device)
{
	debugf1("Releasing device %s\n", dev_name(device));
}

static struct device_type addrmatch_type = {
	.groups		= addrmatch_groups,
	.release	= addrmatch_release,
1113 1114
};

1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
/*
 * all_channel_counts sysfs struct
 */

static struct attribute *i7core_udimm_counters_attrs[] = {
	&dev_attr_udimm0.attr,
	&dev_attr_udimm1.attr,
	&dev_attr_udimm2.attr,
	NULL
};

static struct attribute_group all_channel_counts_grp = {
	.attrs	= i7core_udimm_counters_attrs,
1128 1129
};

1130 1131 1132
static const struct attribute_group *all_channel_counts_groups[] = {
	&all_channel_counts_grp,
	NULL
1133 1134
};

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
static void all_channel_counts_release(struct device *device)
{
	debugf1("Releasing device %s\n", dev_name(device));
}

static struct device_type all_channel_counts_type = {
	.groups		= all_channel_counts_groups,
	.release	= all_channel_counts_release,
};

/*
 * inject sysfs attributes
 */

static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
		   i7core_inject_section_show, i7core_inject_section_store);

static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR,
		   i7core_inject_type_show, i7core_inject_type_store);


static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR,
		   i7core_inject_eccmask_show, i7core_inject_eccmask_store);

static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR,
		   i7core_inject_enable_show, i7core_inject_enable_store);

static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	int rc;

	rc = device_create_file(&mci->dev, &dev_attr_inject_section);
	if (rc < 0)
		return rc;
	rc = device_create_file(&mci->dev, &dev_attr_inject_type);
	if (rc < 0)
		return rc;
	rc = device_create_file(&mci->dev, &dev_attr_inject_eccmask);
	if (rc < 0)
		return rc;
	rc = device_create_file(&mci->dev, &dev_attr_inject_enable);
	if (rc < 0)
		return rc;

	pvt->addrmatch_dev.type = &addrmatch_type;
	pvt->addrmatch_dev.bus = mci->dev.bus;
	device_initialize(&pvt->addrmatch_dev);
	pvt->addrmatch_dev.parent = &mci->dev;
	dev_set_name(&pvt->addrmatch_dev, "inject_addrmatch");
	dev_set_drvdata(&pvt->addrmatch_dev, mci);

	debugf1("%s(): creating %s\n", __func__,
		dev_name(&pvt->addrmatch_dev));

	rc = device_add(&pvt->addrmatch_dev);
	if (rc < 0)
		return rc;

	if (!pvt->is_registered) {
		pvt->chancounts_dev.type = &all_channel_counts_type;
		pvt->chancounts_dev.bus = mci->dev.bus;
		device_initialize(&pvt->chancounts_dev);
		pvt->chancounts_dev.parent = &mci->dev;
		dev_set_name(&pvt->chancounts_dev, "all_channel_counts");
		dev_set_drvdata(&pvt->chancounts_dev, mci);

		debugf1("%s(): creating %s\n", __func__,
			dev_name(&pvt->chancounts_dev));

		rc = device_add(&pvt->chancounts_dev);
		if (rc < 0)
			return rc;
	}
	return 0;
}

static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;

	debugf1("\n");

	device_remove_file(&mci->dev, &dev_attr_inject_section);
	device_remove_file(&mci->dev, &dev_attr_inject_type);
	device_remove_file(&mci->dev, &dev_attr_inject_eccmask);
	device_remove_file(&mci->dev, &dev_attr_inject_enable);

	if (!pvt->is_registered) {
		put_device(&pvt->chancounts_dev);
		device_del(&pvt->chancounts_dev);
	}
	put_device(&pvt->addrmatch_dev);
	device_del(&pvt->addrmatch_dev);
}

1231 1232 1233 1234 1235
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
1236
 *	i7core_put_all_devices	'put' all the devices that we have
1237 1238
 *				reserved via 'get'
 */
1239
static void i7core_put_devices(struct i7core_dev *i7core_dev)
1240
{
Mauro Carvalho Chehab's avatar